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1. 发明授权

US07307905B2 Low leakage asymmetric SRAM cell devices 有权
标题翻译：低泄漏非对称SRAM单元器件
公开(公告)号：US07307905B2
公开(公告)日：2007-12-11
申请号：US10524319
申请日：2003-08-08
申请人： Farid N. Najm , Navid Azizi , Andreas Moshovos
发明人： Farid N. Najm , Navid Azizi , Andreas Moshovos
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C7/067 , G11C7/062 , G11C11/412
摘要： Asymmetric SRAM cell designs exploiting data storage patterns found in ordinary software programs wherein most of the bits stored are zeroes for data and instruction streams. The asymmetric SRAM cell designs offer lower leakage power with little impact on latency. In asymmetric SRAM cells, selected transistors are “weakened” to reduce leakage current when the cell is storing a zero. Transistor weakening may be achieved by using higher voltage threshold transistors, by varying transistor geometries, or other means. In addition, a novel sense amplifier design is provided that leverages the asymmetric nature of the asymmetric SRAM cells to offer cell read times that are comparable with conventional symmetric SRAM cells. Lastly, cache memory designs are provided that are based on asymmetric SRAM cells offering leakage power reduction while maintaining high performance, comparable noise margins, and stability with respect to conventional cache memories.
摘要翻译：非对称SRAM单元设计利用在普通软件程序中发现的数据存储模式，其中存储的大部分位为零，用于数据和指令流。非对称SRAM单元设计提供较低的漏电功率，对延迟影响不大。在非对称SRAM单元中，当单元存储零时，所选择的晶体管被“削弱”以减少泄漏电流。可以通过使用较高电压阈值晶体管，通过改变晶体管几何形状或其他方式来实现晶体管弱化。此外，提供了一种新颖的读出放大器设计，其利用非对称SRAM单元的非对称特性来提供与常规对称SRAM单元相当的单元读取时间。最后，提供基于非对称SRAM单元的缓存存储器设计，其提供泄漏功率降低，同时保持高性能，可比较的噪声容限和相对于常规高速缓冲存储器的稳定性。

2. 发明授权

US06993737B1 Leakage power optimization for integrated circuits 有权
标题翻译：集成电路漏电功率优化
公开(公告)号：US06993737B1
公开(公告)日：2006-01-31
申请号：US10659918
申请日：2003-09-11
申请人： Jason H. Anderson , Farid N. Najm
发明人： Jason H. Anderson , Farid N. Najm
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5054 , G06F2217/78
摘要： A method for reducing leakage power in a system comprises determining the static probability for a signal in the system. If the static probability of the signal is in a high power range, then the signal is modified such that the static probability of the modified signal is in a low power range, and such that functionality of the system is not affected. In some embodiments, where the signal is a digital signal, modifying the signal comprises inverting the signal. In some embodiments, where the system comprises a programmable logic device, modifying the signal has no area or performance penalty.
摘要翻译：一种用于减少系统中的泄漏功率的方法包括确定系统中的信号的静态概率。如果信号的静态概率在高功率范围内，则修改信号，使得修改的信号的静态概率处于低功率范围，并且使得系统的功能不受影响。在一些实施例中，在信号是数字信号的情况下，修改信号包括反转信号。在一些实施例中，在系统包括可编程逻辑器件的情况下，修改该信号没有面积或性能损失。

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