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    • 1. 发明授权
    • Information processing device
    • 信息处理装置
    • US08484448B2
    • 2013-07-09
    • US13399023
    • 2012-02-17
    • Motokazu OzawaNaohiko IrieSaneaki TamakiHisayoshi IdeMiki Hayakawa
    • Motokazu OzawaNaohiko IrieSaneaki TamakiHisayoshi IdeMiki Hayakawa
    • G06F9/00G06F15/177
    • G06F1/3203G06F1/3243G06F1/3287Y02D10/152Y02D10/171Y02D50/20
    • Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.
    • 信息处理系统,包括具有低于第一操作电流的第一操作模式和第二操作模式,当引导地址寄存器从第二操作模式返回到第一操作模式时,首先保存由处理单元执行的指令的地址的寄存器,其中该地址为 当第二至第一操作模式转换时,输出到处理单元,其中引导地址寄存器是可重写的,信息保持电路保持外围电路模块寄存器的值,其中信息保持电路在第二操作模式中保持关于 外围电路模块寄存器,并且将关于第二至第一操作模式移位的信息保持电路中保存的信息传送到外围电路模块寄存器,并且其中当在第二操作模式中从系统外部发布中断请求时 信息处理系统执行与内部相对应的中断处理 破产请求
    • 2. 发明申请
    • INFORMATION PROCESSING DEVICE
    • 信息处理设备
    • US20120151197A1
    • 2012-06-14
    • US13399023
    • 2012-02-17
    • Motokazu OzawaNaohiko IrieSaneaki TamakiHisayoshi IdeMiki Hayakawa
    • Motokazu OzawaNaohiko IrieSaneaki TamakiHisayoshi IdeMiki Hayakawa
    • G06F9/00
    • G06F1/3203G06F1/3243G06F1/3287Y02D10/152Y02D10/171Y02D50/20
    • Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.
    • 信息处理系统,包括具有低于第一操作电流的第一操作模式和第二操作模式,当引导地址寄存器从第二操作模式返回到第一操作模式时,首先保存由处理单元执行的指令的地址的寄存器,其中该地址为 当第二至第一操作模式转换时,输出到处理单元,其中引导地址寄存器是可重写的,信息保持电路保持外围电路模块寄存器的值,其中信息保持电路在第二操作模式中保持关于 外围电路模块寄存器,并且将关于第二至第一操作模式移位的信息保持电路中保存的信息传送到外围电路模块寄存器,并且其中当在第二操作模式中从系统外部发布中断请求时 信息处理系统执行与内部相对应的中断处理 破产请求
    • 3. 发明授权
    • Handover between software and hardware accelerator
    • 软件和硬件加速器之间切换
    • US07853776B2
    • 2010-12-14
    • US11260423
    • 2005-10-28
    • Tetsuya YamadaNaohiko Irie
    • Tetsuya YamadaNaohiko Irie
    • G06F9/30
    • G06F9/30174
    • A bytecode accelerator which translates stack-based intermediate language (bytecodes) into register-based CPU instructions transfers plural pieces of internal information from a register file of a CPU to the bytecode accelerator by means of an internal transfer bus between the bytecode accelerator and the CPU and an input selection logic of the bytecode accelerator when the bytecode accelerator is started and transfers plural pieces of internal information in the bytecode accelerator to the register file of the CPU by means of the internal transfer bus, an output selector and an output selector selection logic of the bytecode accelerator when the bytecode accelerator ends its operation in transition between hardware processing and software processing by software virtual machine.
    • 将基于堆栈的中间语言(字节码)转换为基于寄存器的CPU指令的字节码加速器通过字节码加速器和CPU之间的内部传输总线将多条内部信息从CPU的寄存器文件传送到字节码加速器 以及当字节代码加速器启动时字节码加速器的输入选择逻辑,并且通过内部传送总线,输出选择器和输出选择器选择逻辑,将字节码加速器中的多条内部信息传送到CPU的寄存器文件 字节码加速器在硬件处理和软件虚拟机的软件处理之间的转换中结束其操作。
    • 5. 发明授权
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US07612391B2
    • 2009-11-03
    • US12236170
    • 2008-09-23
    • Yusuke KannoHiroyuki MizunoNaohiko Irie
    • Yusuke KannoHiroyuki MizunoNaohiko Irie
    • H01L23/50
    • G01R31/318572G11C5/063G11C11/417H01L27/0207H01L27/092H01L27/11807H01L2924/0002H03K3/356008H03K3/35625H03K19/0016H01L2924/00
    • In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefore for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.
    • 在功率关闭时保留先前数据的低功耗模式下,其返回速度增加。 虽然可以考虑使用现有的数据保持触发器,但是这不是优选的,因为它增加了诸如扩大单元大小的面积开销。 用于电源关闭的数据保持的电源线由比通常的主电源线更细的布线形成。 优选地,用于数据保持电路的电力线被认为是信号线,并通过自动放置和安装进行布线。 为此,预先通过以与现有信号线相同的方式为单元提供端子来设计用于数据保持的电力线的端子。 电池线的附加布局不再需要,这使得现有的放置和布线工具能够减少面积和设计。
    • 7. 发明申请
    • Multiprocessor system
    • 多处理器系统
    • US20060085582A1
    • 2006-04-20
    • US11203284
    • 2005-08-15
    • Hiroaki ShikanoNaohiko Irie
    • Hiroaki ShikanoNaohiko Irie
    • G06F13/24
    • G06F13/24
    • An interrupt notification network is provided for a multiprocessor system in which many processor units are installed. An interrupt notification source processor unit transmits an interrupt notification packet to an interrupt notification destination processor unit. The interrupt notification packet to be transmitted by the interrupt notification source processor unit contains an interrupt destination process ID. A control section for the interrupt notification network analyzes the transmitted interrupt notification packet, references a table that defines the correspondence between internally retained IDs of processes and processor units that perform the processes, determines the interrupt notification destination processor unit, and transmits the interrupt notification packet to the processor unit. Consequently, the multiprocessor system in which many processor units are installed is capable of performing an inter-processor unit multiplex coordination process for inter-processor unit process synchronization and process control, increasing the system throughput, and providing increased real-time capability.
    • 为其中安装许多处理器单元的多处理器系统提供中断通知网络。 中断通知源处理器单元向中断通知目的地处理器单元发送中断通知分组。 要由中断通知源处理器单元发送的中断通知包含有中断目的地处理ID。 用于中断通知网络的控制部分分析发送的中断通知分组,引用定义进程的内部保留ID和处理器单元之间的对应关系的表,确定中断通知目的地处理器单元,并发送中断通知分组 到处理器单元。 因此,其中安装有许多处理器单元的多处理器系统能够执行用于处理器间单元处理同步和过程控制的处理器间单元复用协调处理,增加系统吞吐量并提供增加的实时能力。