专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2011007976A2 SEA-CLEANING SHIP 审中-公开
标题翻译：海洋清洁船
公开(公告)号：WO2011007976A2
公开(公告)日：2011-01-20
申请号：PCT/KR2010004357
申请日：2010-07-05
申请人： ILSHIN EMTECH , SUNG BAEK WOO , SOHN MOO JEONG
发明人： SUNG BAEK WOO , SOHN MOO JEONG
IPC分类号： B63B35/32 , E02B15/04
CPC分类号： B63B35/32 , E02B15/046 , E02B15/104 , Y02A20/204
摘要： The present invention relates to a sea-cleaning ship which can remove oil and miscellaneous articles from a sea, a harbor, and the surface of inland waters. The ship of the present invention comprises: a hull having a waterway for draining water which is introduced from the stem of the hull and flows toward the stern of the hull, and a guide floodgate which vertically penetrates through the center of the waterway; a screen member installed at the stem of the hull to remove miscellaneous articles introduced through the waterway and to maintain a wave at a constant height; a floating floodgate movably arranged in a vertical direction in the guide floodgate by buoyant force to drain water while shutting off the flow of the floating oil passing through the screen member; at least one oil skimmer interposed between the floating floodgate and the screen member to suction the oil shut off by the floating floodgate; and an oil separator connected to the oil skimmer to separate water from the oil suctioned by the oil skimmer. Consequently, the present invention removes miscellaneous articles from a sea, a harbor, and the surface of inland waters, and removes the oil shut off by the floating floodgate using the oil skimmer, thereby automatically and conveniently removing oil and miscellaneous articles.
摘要翻译：本发明涉及一种能够从海洋，港口和内陆水域的表面去除油和杂物的海水清洁船。本发明的船舶包括：船体，其具有用于从船体的船首引入并流向船体尾部的水的排水道和垂直穿过水道中心的引导水闸; 安装在船身杆上的筛网件，用于去除通过水道引入的杂项物品并保持恒定高度的波浪; 一个浮动闸门，通过浮力在垂直方向上可移动地布置在导向闸门内，以排出水，同时关闭通过筛网构件的浮动油的流动; 至少一个撇油器，介于浮动闸门和筛网部件之间以吸入由浮动闸门关闭的油; 以及连接至撇油器的油分离器，以将油从撇油器吸入的油中分离出来。因此，本发明从海洋，港口和内陆水域的表面去除杂项物品，并且使用油撇取器去除由浮动闸门关闭的油，由此自动且方便地去除油和杂项物品。

2. 发明申请

US20110222156A1 Diffractive Element for Optical Pickup and Optical Module Including the Same 审中-公开
$Diffractive Element for Optical Pickup and Optical Module Including the Same$
标题翻译：用于光学拾取的衍射元件和包括其的光学模块
公开(公告)号：US20110222156A1
公开(公告)日：2011-09-15
申请号：US12755750
申请日：2010-04-07
申请人： Byeong Moo Jeong , Kyung Ho Jung
发明人： Byeong Moo Jeong , Kyung Ho Jung
IPC分类号： G02B5/18
CPC分类号： G02B5/1814 , G11B7/1353 , G11B7/22
摘要： Provided are a diffractive element for optical pickup and an optical module including the diffractive element. The diffractive element includes a plurality of diffraction patterns, and the diffraction patterns include a main diffraction pattern for creating diffraction characteristics, and an alignment mark pattern for recognizing an alignment position, the alignment mark pattern having a different pitch from the main diffraction pattern. Also, the pitch of the alignment mark pattern is formed smaller than that of the main diffraction pattern. Further, a ratio of the pitch of the alignment mark pattern to that of the main diffraction pattern is ⅛ or greater to ½ or less.
摘要翻译：提供了一种用于光学拾取器的衍射元件和包括该衍射元件的光学模块。衍射元件包括多个衍射图案，衍射图案包括用于产生衍射特性的主衍射图案和用于识别取向位置的对准标记图案，该对准标记图案与主衍射图案具有不同的间距。此外，对准标记图案的间距形成为小于主衍射图案的间距。此外，对准标记图案的间距与主衍射图案的间距的比率为⅛以上至½以下。

3. 发明申请

US20060111103A1 Fast active scanning wireless network apparatus and method 有权
标题翻译：快速主动扫描无线网络设备及方法
公开(公告)号：US20060111103A1
公开(公告)日：2006-05-25
申请号：US10545466
申请日：2004-04-02
申请人： Moo Jeong , Fujio Watanabe , Toshiro Kawahara
发明人： Moo Jeong , Fujio Watanabe , Toshiro Kawahara
IPC分类号： H04Q7/20
CPC分类号： H04W48/14 , H04B7/022 , H04W48/16 , H04W48/20 , H04W74/08 , H04W84/12
摘要： In a fast active scanning wireless network apparatus and method for quick determination of available access points (20), information about a candidate set of available access points (20) is obtained, and a candidate access point is identified from the candidate set. A mobile station (10) then queries the candidate access point with a probe request that designates the candidate access point as a sole responder. The probe request prevents other access points from contending for the medium of communication between the mobile station and the designated sole responder access point by excluding the attempt by other access points (20) to transmit probe responses. The apparatus and method thus increases the probability of a fast and successful probe request from the mobile station and subsequent response from the designated access point (20). The designated access point may also respond with a probe response of high priority, preventing intervention of communication.
摘要翻译：在用于快速确定可用接入点（20）的快速主动扫描无线网络装置和方法中，获得关于可用接入点（20）的候选集合的信息，并且从候选集合识别候选接入点。然后，移动站（10）用指定候选接入点的探测请求作为唯一响应者来查询候选接入点。探测请求通过排除其他接入点（20）发送探测响应的尝试来防止其他接入点竞争移动台和指定的唯一响应者接入点之间的通信介质。因此，装置和方法增加了来自移动台的快速和成功的探测请求的概率以及从指定接入点（20）的后续响应。指定的接入点也可以以高优先级的探测响应进行响应，防止通信干扰。

4. 发明申请

US20080069349A1 Device and method for generating chaotic signal 有权
标题翻译：用于产生混沌信号的装置和方法
公开(公告)号：US20080069349A1
公开(公告)日：2008-03-20
申请号：US11889326
申请日：2007-08-10
申请人： Yu Kim , No Myung , Jeong Moon , Moo Jeong , Chang Lee , Chang Yang , Kwang Lee , Sang Park
发明人： Yu Kim , No Myung , Jeong Moon , Moo Jeong , Chang Lee , Chang Yang , Kwang Lee , Sang Park
IPC分类号： H04L9/22
CPC分类号： H03K3/84 , H04B1/69 , H04B1/71632 , H04B1/7174 , H04L27/04
摘要： Provided is a device for generating a chaotic signal comprising a PN signal generator that is composed of a digital logic circuit and generates a digital pseudo random signal with a predetermined frequency; a voltage control that generates a clock signal with a predetermined frequency; a mixer that mixes the pseudo random signal and the clock signal so as to generate a chaotic signal to output; and a band-pass filter that filters the chaotic signal, output from the mixer, into a chaotic signal of a desired band and then outputs the filtered signal.
摘要翻译：提供一种用于产生混沌信号的装置，包括由数字逻辑电路组成的PN信号发生器，并产生具有预定频率的数字伪随机信号; 产生具有预定频率的时钟信号的电压控制; 混合器，混合伪随机信号和时钟信号，以产生混沌信号输出; 以及带通滤波器，其将从混频器输出的混沌信号滤波成期望频带的混沌信号，然后输出滤波后的信号。

5. 发明授权

US07297998B2 Semiconductor devices having a buried and enlarged contact hole and methods of fabricating the same 有权
标题翻译：具有埋入和扩大的接触孔的半导体器件及其制造方法
公开(公告)号：US07297998B2
公开(公告)日：2007-11-20
申请号：US11419719
申请日：2006-05-22
申请人： Seong-Goo Kim , Sang-Moo Jeong
发明人： Seong-Goo Kim , Sang-Moo Jeong
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L21/76895 , H01L21/76804 , H01L21/76831 , H01L21/76897 , H01L23/485 , H01L27/10814 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit line and a bit line capping layer pattern stacked thereon. A buried contact interlayer insulating layer covers a surface of the semiconductor substrate having the two adjacent bit line patterns. A contact hole is placed in a portion between the bit line patterns to penetrate the buried contact interlayer insulating layer and the bit line interlayer insulating layer and to expose at least one side wall of the bit line patterns. A contact hole spacer covers side wall of the contact hole. A contact hole plug is placed on the contact hole spacer to fill the contact hole.
摘要翻译：根据本发明的实施例，将位线层间绝缘层放置在半导体衬底上。两个相邻位线图案并联放置在位线层间绝缘层上，并且两个相邻位线图案中的每一个都包括位线和位线叠层层图案。掩埋接触层间绝缘层覆盖具有两个相邻位线图案的半导体衬底的表面。接触孔放置在位线图案之间的部分中，以穿透埋入层间绝缘层和位线层间绝缘层，并露出位线图案的至少一个侧壁。接触孔间隔件覆盖接触孔的侧壁。接触孔插头放置在接触孔间隔件上以填充接触孔。

6. 发明申请

US20070059610A1 Method of making and designing dummy patterns for semiconductor devices and semiconductor devices having dummy patterns 审中-公开
标题翻译：制造和设计具有虚拟图形的半导体器件和半导体器件的虚拟图案的方法
公开(公告)号：US20070059610A1
公开(公告)日：2007-03-15
申请号：US11414700
申请日：2006-04-28
申请人： Sang-Moo Jeong , Sun-Hoo Park , Dong-Hyun Han
发明人： Sang-Moo Jeong , Sun-Hoo Park , Dong-Hyun Han
IPC分类号： G03F1/00
CPC分类号： H01L21/7684 , G03F1/36 , H01L21/3212 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with dummy patterns and methods of designing and making dummy patterns of a semiconductor device are provided. The method includes forming a first layout having main patterns, adding dot dummy patterns to the first layout to generate a second layout, and adding linked line/space dummy patterns to the second layout to generate a third layout. The dot dummy patterns may be oblique dot dummy patterns.
摘要翻译：提供具有虚拟图案的半导体器件以及设计和制造半导体器件的虚拟图案的方法。该方法包括形成具有主图案的第一布局，将第一布局添加点虚拟图案以生成第二布局，以及将链接的线/空虚拟图案添加到第二布局以生成第三布局。点虚拟图案可以是斜点虚拟图案。

7. 发明申请

US20060197162A1 SEMICONDUCTOR DEVICES HAVING A BURIED AND ENLARGED CONTACT HOLE AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有凸起和放大的接触孔的半导体器件及其制造方法
公开(公告)号：US20060197162A1
公开(公告)日：2006-09-07
申请号：US11419719
申请日：2006-05-22
申请人： Seong-Goo KIM , Sang-Moo JEONG
发明人： Seong-Goo KIM , Sang-Moo JEONG
IPC分类号： H01L29/76
CPC分类号： H01L21/76895 , H01L21/76804 , H01L21/76831 , H01L21/76897 , H01L23/485 , H01L27/10814 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit line and a bit line capping layer pattern stacked thereon. A buried contact interlayer insulating layer covers a surface of the semiconductor substrate having the two adjacent bit line patterns. A contact hole is placed in a portion between the bit line patterns to penetrate the buried contact interlayer insulating layer and the bit line interlayer insulating layer and to expose at least one side wall of the bit line patterns. A contact hole spacer covers side wall of the contact hole. A contact hole plug is placed on the contact hole spacer to fill the contact hole.
摘要翻译：根据本发明的实施例，将位线层间绝缘层放置在半导体衬底上。两个相邻位线图案并联放置在位线层间绝缘层上，并且两个相邻位线图案中的每一个都包括位线和位线叠层层图案。掩埋接触层间绝缘层覆盖具有两个相邻位线图案的半导体衬底的表面。接触孔放置在位线图案之间的部分中，以穿透埋入层间绝缘层和位线层间绝缘层，并露出位线图案的至少一个侧壁。接触孔间隔件覆盖接触孔的侧壁。接触孔插头放置在接触孔间隔件上以填充接触孔。

8. 发明授权

US07074718B2 Method of fabricating a semiconductor device having a buried and enlarged contact hole 有权
标题翻译：制造具有埋入和扩大的接触孔的半导体器件的方法
公开(公告)号：US07074718B2
公开(公告)日：2006-07-11
申请号：US10898485
申请日：2004-07-22
申请人： Seong-Goo Kim , Sang-Moo Jeong
发明人： Seong-Goo Kim , Sang-Moo Jeong
IPC分类号： H01L21/4763 , H01L21/336 , H01L21/331 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76895 , H01L21/76804 , H01L21/76831 , H01L21/76897 , H01L23/485 , H01L27/10814 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit line and a bit line capping layer pattern stacked thereon. A buried contact interlayer insulating layer covers a surface of the semiconductor substrate having the two adjacent bit line patterns. A contact hole is placed in a portion between the bit line patterns to penetrate the buried contact interlayer insulating layer and the bit line interlayer insulating layer and to expose at least one side wall of the bit line patterns. A contact hole spacer covers side wall of the contact hole. A contact hole plug is placed on the contact hole spacer to fill the contact hole.
摘要翻译：根据本发明的实施例，将位线层间绝缘层放置在半导体衬底上。两个相邻位线图案并联放置在位线层间绝缘层上，并且两个相邻位线图案中的每一个都包括位线和位线叠层层图案。掩埋接触层间绝缘层覆盖具有两个相邻位线图案的半导体衬底的表面。接触孔放置在位线图案之间的部分中，以穿透埋入层间绝缘层和位线层间绝缘层，并露出位线图案的至少一个侧壁。接触孔间隔件覆盖接触孔的侧壁。接触孔插头放置在接触孔间隔件上以填充接触孔。

9. 发明申请

US20050232200A1 Method and apparatus for dormant mode support with paging 失效
标题翻译：用寻呼方式支持休眠模式的方法和装置
公开(公告)号：US20050232200A1
公开(公告)日：2005-10-20
申请号：US11153032
申请日：2005-06-14
申请人： Moo Jeong , Fujio Watanabe , Toshiro Kawahara
发明人： Moo Jeong , Fujio Watanabe , Toshiro Kawahara
IPC分类号： H04L12/28 , H04L12/56 , H04W36/08 , H04W52/02 , H04W68/00 , H04Q7/00
CPC分类号： H04W68/00 , H04W36/08 , H04W52/0216 , H04W60/04 , Y02D70/142
摘要： A method and communication system for supporting dormant mode are described. In one embodiment, the communication system comprises a wireless station operable in a power savings mode and group of access points. Each group of access points comprises one or more access points with at least one group of access points having at least two access points. Ranges for the one or more access points in each of the groups define a paging area for each group, wherein one access point uses a paging channel for paging the wireless station when the wireless station is in the power savings mode and is in the paging area associated with the one access point. The wireless station performs a handoff procedure when the one access point is not in the same group of access points as the access point associated with the wireless station prior to the wireless station entering the power savings mode and does not perform a handoff procedure when the one access point is in the same group of access points as the access point associated with the wireless station prior to the wireless station entering the power savings mode.
摘要翻译：描述了用于支持休眠模式的方法和通信系统。在一个实施例中，通信系统包括可在功率节省模式和接入点组中操作的无线站。每组接入点包括一个或多个接入点，其中至少一组接入点具有至少两个接入点。每个组中的一个或多个接入点的范围定义每个组的寻呼区域，其中当无线站处于省电模式并且处于寻呼区域中时，一个接入点使用寻呼信道来寻呼无线站与一个接入点相关联。当无线站进入省电模式之前，当一个接入点不与与无线站相关联的接入点的接入点不在同一组接入点时，无线站执行切换过程，并且当一个接入点不执行切换过程时在无线站进入省电模式之前，接入点与与无线站相关联的接入点处于同一组接入点。

10. 发明申请

US20050017295A1 Semiconductor devices having a buried and enlarged contact hole and methods of fabricating the same 有权
标题翻译：具有埋入和扩大的接触孔的半导体器件及其制造方法
公开(公告)号：US20050017295A1
公开(公告)日：2005-01-27
申请号：US10898485
申请日：2004-07-22
申请人： Seong-Goo Kim , Sang-Moo Jeong
发明人： Seong-Goo Kim , Sang-Moo Jeong
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L27/108 , H01L29/76
CPC分类号： H01L21/76895 , H01L21/76804 , H01L21/76831 , H01L21/76897 , H01L23/485 , H01L27/10814 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit line and a bit line capping layer pattern stacked thereon. A buried contact interlayer insulating layer covers a surface of the semiconductor substrate having the two adjacent bit line patterns. A contact hole is placed in a portion between the bit line patterns to penetrate the buried contact interlayer insulating layer and the bit line interlayer insulating layer and to expose at least one side wall of the bit line patterns. A contact hole spacer covers side wall of the contact hole. A contact hole plug is placed on the contact hole spacer to fill the contact hole.
摘要翻译：根据本发明的实施例，将位线层间绝缘层放置在半导体衬底上。两个相邻位线图案并联放置在位线层间绝缘层上，并且两个相邻位线图案中的每一个都包括位线和位线叠层层图案。掩埋接触层间绝缘层覆盖具有两个相邻位线图案的半导体衬底的表面。接触孔放置在位线图案之间的部分中，以穿透埋入层间绝缘层和位线层间绝缘层，并露出位线图案的至少一个侧壁。接触孔间隔件覆盖接触孔的侧壁。接触孔插头放置在接触孔间隔件上以填充接触孔。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式