专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070059610A1 Method of making and designing dummy patterns for semiconductor devices and semiconductor devices having dummy patterns 审中-公开
标题翻译：制造和设计具有虚拟图形的半导体器件和半导体器件的虚拟图案的方法
公开(公告)号：US20070059610A1
公开(公告)日：2007-03-15
申请号：US11414700
申请日：2006-04-28
申请人： Sang-Moo Jeong , Sun-Hoo Park , Dong-Hyun Han
发明人： Sang-Moo Jeong , Sun-Hoo Park , Dong-Hyun Han
IPC分类号： G03F1/00
CPC分类号： H01L21/7684 , G03F1/36 , H01L21/3212 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with dummy patterns and methods of designing and making dummy patterns of a semiconductor device are provided. The method includes forming a first layout having main patterns, adding dot dummy patterns to the first layout to generate a second layout, and adding linked line/space dummy patterns to the second layout to generate a third layout. The dot dummy patterns may be oblique dot dummy patterns.
摘要翻译：提供具有虚拟图案的半导体器件以及设计和制造半导体器件的虚拟图案的方法。该方法包括形成具有主图案的第一布局，将第一布局添加点虚拟图案以生成第二布局，以及将链接的线/空虚拟图案添加到第二布局以生成第三布局。点虚拟图案可以是斜点虚拟图案。

2. 发明授权

US06774048B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06774048B2
公开(公告)日：2004-08-10
申请号：US10346792
申请日：2003-01-17
申请人： Eun-Kyung Baek , Sun-Hoo Park , Hong-Gun Kim , Kyung-Joong Yoon
发明人： Eun-Kyung Baek , Sun-Hoo Park , Hong-Gun Kim , Kyung-Joong Yoon
IPC分类号： H01L2131
CPC分类号： H01L21/0217 , H01L21/02164 , H01L21/022 , H01L21/02321 , H01L21/0234 , H01L21/31116 , H01L21/3144 , H01L21/3145 , H01L21/8234
摘要： A method of manufacturing a semiconductor device includes forming a silicon nitride layer on a semiconductor substrate on which a predetermined pattern is formed. The silicon nitride layer includes a plurality of bonds formed between silicon and nitrogen. A portion of the bonds formed between silicon and nitrogen is broken to form at least one free bonding site on a surface of the silicon nitride layer. A silane compound and a flow fill method are used to form a silicon oxide layer on the silicon nitride layer.
摘要翻译：制造半导体器件的方法包括在其上形成有预定图案的半导体衬底上形成氮化硅层。氮化硅层包括在硅和氮之间形成的多个键。在硅和氮之间形成的键的一部分被破坏以在氮化硅层的表面上形成至少一个自由键合位置。硅烷化合物和流动填充法用于在氮化硅层上形成氧化硅层。

3. 发明授权

US07749846B2 Method of forming contact structure and method of fabricating semiconductor device using the same 有权
标题翻译：形成接触结构的方法和使用其制造半导体器件的方法
公开(公告)号：US07749846B2
公开(公告)日：2010-07-06
申请号：US12048145
申请日：2008-03-13
申请人： Hyeoung-Won Seo , Sun-Hoo Park , Soo-Ho Shin
发明人： Hyeoung-Won Seo , Sun-Hoo Park , Soo-Ho Shin
IPC分类号： H01L21/00
CPC分类号： H01L21/76897 , H01L27/10876 , H01L27/10888
摘要： A method of forming a contact structure includes forming an isolation region defining active regions in a semiconductor substrate. Gate patterns extending to the isolation region while crossing the active regions are formed. A sacrificial layer is formed on the semiconductor substrate having the gate patterns. Sacrificial patterns remaining on the active regions are formed by patterning the sacrificial layer. Molding patterns are formed on the isolation region. Contact holes exposing the active regions at both sides of the gate patterns are formed by etching the sacrificial patterns using the molding patterns and the gate patterns as an etching mask. Contact patterns respectively filling the contact holes are formed. The disclosed method of forming a contact structure may be used in fabricating a semiconductor device.
摘要翻译：形成接触结构的方法包括在半导体衬底中形成限定有源区的隔离区。形成了跨越有源区域延伸到隔离区域的栅极图案。在具有栅极图案的半导体衬底上形成牺牲层。通过图案化牺牲层来形成残留在有源区上的牺牲图案。在隔离区上形成成型图案。通过使用模制图案和栅极图案作为蚀刻掩模蚀刻牺牲图案来形成暴露栅极图案两侧的有源区的接触孔。形成分别填充接触孔的接触图案。所公开的形成接触结构的方法可用于制造半导体器件。

4. 发明申请

US20090019983A1 PINNACLE DIE STRUCTURE HAVING SCRAP COLLECTING OPENING 审中-公开
标题翻译：具有切片收集开口的PINNACLE DIE结构
公开(公告)号：US20090019983A1
公开(公告)日：2009-01-22
申请号：US11572552
申请日：2006-07-01
申请人： Sun-Hoo Park
发明人： Sun-Hoo Park
IPC分类号： B26F1/44
CPC分类号： B21D28/26 , Y10T83/242 , Y10T83/9423 , Y10T83/9454
摘要： Disclosed herein is a pinnacle die structure having a scrap collecting opening. The pinnacle die structure comprises a pinnacle die(100), which includes a supporting plate(10) integrally formed with a cutter blade(20) and at least one hole-processing pin(30). The hole-processing pin is internally formed with a scrap discharge hole(32) to discharge a scrap(202) of a material sheet(200) punched by the pinnacle die. A scrap collecting opening(40) is defined above the hole-processing pin to collect the scrap discharged from the scrap discharge hole.
摘要翻译：本文公开了具有废料收集口的顶点模具结构。所述巅峰模具结构包括巅峰模具（100），其包括与切割刀片（20）一体形成的支撑板（10）和至少一个孔加工销（30）。孔加工销内部形成有废料排出孔（32），以排出由顶点冲压的材料片（200）的废料（202）。废料收集口（40）被限定在孔加工销的上方，以收集从废料排出孔排出的废料。

5. 发明授权

US06756292B2 Method of forming a quantum dot and a gate electrode using the same 有权
标题翻译：使用该方法形成量子点和栅电极的方法
公开(公告)号：US06756292B2
公开(公告)日：2004-06-29
申请号：US10243956
申请日：2002-09-16
申请人： Jang-Eun Lee , Sun-Hoo Park , Jung-Hoon Son
发明人： Jang-Eun Lee , Sun-Hoo Park , Jung-Hoon Son
IPC分类号： H01L21477
CPC分类号： B82Y20/00 , H01L27/105 , H01L27/1052 , H01L27/10873 , Y10S438/962
摘要： In a method of forming a quantum dot having nanometeric size and a method of forming a gate electrode including the quantum dot, a first layer including a first material is deposited on the substrate. The first material has first atoms that are superbundant and bound with the weak bonding energy in the first layer. A second layer is deposited on the first layer. The second layer comprises a second material including second atoms that are capable of migrating into the first atoms. The first atoms are migrated into the second layer and the second atoms are migrated into the first layer, so that the second atoms are arranged in the first layer. Each of the second atoms in the first layer is formed into a quantum dot. An electrode layer is formed on the first layer after partially etching the second layer, and then a gate electrode is formed by patterning the electrode layer. Accordingly, The quantum dot can be formed in the semiconductor device in such a manner that a size and a distribution of the quantum dot is easily controlled.
摘要翻译：在形成具有纳米尺寸的量子点的方法和形成包括量子点的栅电极的方法中，在基板上沉积包括第一材料的第一层。第一种材料具有超第一原子，并与第一层中的弱键合能结合。第二层沉积在第一层上。第二层包括第二材料，其包括能够迁移到第一原子中的第二原子。第一原子迁移到第二层中，第二原子迁移到第一层中，使得第二原子排列在第一层中。第一层中的每个第二原子形成量子点。在部分蚀刻第二层之后，在第一层上形成电极层，然后通过图案化电极层形成栅电极。因此，可以以量子点的尺寸和分布容易地控制的方式在半导体器件中形成量子点。

6. 发明授权

US07629215B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07629215B2
公开(公告)日：2009-12-08
申请号：US12128682
申请日：2008-05-29
申请人： Soo-Ho Shin , Sun-Hoo Park , Byung-Hyug Roh , Young-Woong Son , Sang-Wook Lee
发明人： Soo-Ho Shin , Sun-Hoo Park , Byung-Hyug Roh , Young-Woong Son , Sang-Wook Lee
IPC分类号： H01L21/8238 , H01L31/062
CPC分类号： H01L21/823468 , H01L21/823425 , H01L21/823456 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： A semiconductor device includes first gate structures, second gate structures, a first capping layer pattern, a second capping layer pattern, first spacers, second spacers, third spacers, and a substrate having first impurity regions and second impurity regions. The first gate structures are arranged on the substrate at a first pitch. The second gate structures are arranged on the substrate at a second pitch greater than the first pitch. The first capping layer pattern has segments extending along side faces of the first gate structures and segments extending along the substrate. The second capping layer pattern has segments extending along the second gate structures and segments extending along the substrate. The first spacers and the second spacers are stacked on the second capping layer pattern. The third spacers are formed on the first capping layer pattern.
摘要翻译：半导体器件包括第一栅极结构，第二栅极结构，第一覆盖层图案，第二覆盖层图案，第一间隔物，第二间隔物，第三间隔物以及具有第一杂质区和第二杂质区的衬底。第一栅极结构以第一间距布置在衬底上。第二栅极结构以大于第一间距的第二间距布置在衬底上。第一覆盖层图案具有沿着第一栅极结构的侧面延伸的段和沿着衬底延伸的段。第二覆盖层图案具有沿着第二栅极结构延伸的段和沿着衬底延伸的段。第一间隔物和第二间隔物层叠在第二覆盖层图案上。第三间隔物形成在第一覆盖层图案上。

7. 发明授权

US06372555B1 Semiconductor integrated circuit device and method of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06372555B1
公开(公告)日：2002-04-16
申请号：US09399926
申请日：1999-09-21
申请人： Seung-Jae Lee , Tae-Wook Seo , Sun-Hoo Park
发明人： Seung-Jae Lee , Tae-Wook Seo , Sun-Hoo Park
IPC分类号： H01L2182
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A novel fuse structure for a semiconductor integrated circuit device and the method of manufacturing the semiconductor integrated circuit device is disclosed. The fuse structure is comprised of a first interconnection metal layer formed on a semiconductor substrate; an inter-metal dielectric layer formed on the first interconnection metal layer having a via exposing the first interconnection metal layer; a via plug filling up the via; a metal layer for a fuse and a second interconnection metal layer consecutively deposited on the via plug and the inter-metal dielectric layer; and an opening area exposing the metal layer for a fuse is positioned more than twice the thickness of the second interconnection metal layer from the via. With the present invention, a contact failure which can result from a damage to via plug in a subsequent stripping step can be prevented. Also, a passivation layer formed after opening the fuse area prevents a short-circuit between adjacent fuses in a subsequent laser repairing process.
摘要翻译：公开了一种用于半导体集成电路器件的新型熔丝结构和半导体集成电路器件的制造方法。熔丝结构由形成在半导体衬底上的第一互连金属层构成; 在所述第一互连金属层上形成的金属间介电层，其具有暴露所述第一互连金属层的通孔; 通孔插入通孔; 用于保险丝的金属层和连续地沉积在通孔插塞和金属间介电层上的第二互连金属层; 并且露出用于保险丝的金属层的开口面积比第二互连金属层从通孔的厚度的两倍以上。利用本发明，可以防止在随后的剥离步骤中由通孔堵塞造成的接触故障。此外，在打开保险丝区域之后形成的钝化层在随后的激光修复过程中防止相邻熔丝之间的短路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式