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1. 发明授权

US06603680B2 Semiconductor device and data processing system 失效
标题翻译：半导体器件和数据处理系统
公开(公告)号：US06603680B2
公开(公告)日：2003-08-05
申请号：US10013538
申请日：2001-12-13
申请人： Michitaro Kanamitsu , Yoshinori Takase
发明人： Michitaro Kanamitsu , Yoshinori Takase
IPC分类号： G11C1604
CPC分类号： G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C2211/5642
摘要： The present invention provides a semiconductor device such as a multi-valued flash memory or the like, which is capable of shortening a processing time required to set write control information to a sense latch. The semiconductor device is capable of electrically writing multi-value information therein. Bit lines are connected to the right and left input/output terminals of a sense latch, and data latches are connected to the respective bit lines. A decoder is provided which decodes write data supplied from outside to thereby generate write control information. The write control information is latched in each of the sense latch and data latches, and the latched control information is set as information indicative of go/no-go of the application of a write voltage, which corresponds to each value in a multivalue.
摘要翻译：本发明提供了诸如多值闪存等的半导体器件，其能够缩短将写入控制信息设置到感测锁存器所需的处理时间。半导体器件能够在其中写入多值信息。位线连接到检测锁存器的右和左输入/输出端子，数据锁存器连接到相应的位线。提供一种解码器，其解码从外部提供的写入数据，从而生成写入控制信息。写入控制信息被锁存在每个读出锁存器和数据锁存器中，并且锁存的控制信息被设置为指示施加写入电压的去/不去的信息，其对应于多值中的每个值。

2. 发明授权

US06567315B2 Nonvolatile memory and method of programming the same memory 有权
公开(公告)号：US06567315B2
公开(公告)日：2003-05-20
申请号：US10012549
申请日：2001-12-12
申请人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
发明人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12
摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

3. 发明授权

US07616516B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07616516B2
公开(公告)日：2009-11-10
申请号：US12109339
申请日：2008-04-24
申请人： Masayuki Hirayama , Masami Hasegawa , Michitaro Kanamitsu , Yayoi Hayashi , Naoyuki Anan
发明人： Masayuki Hirayama , Masami Hasegawa , Michitaro Kanamitsu , Yayoi Hayashi , Naoyuki Anan
IPC分类号： G11C5/14
CPC分类号： G11C11/412
摘要： A semiconductor device of the present invention has a memory cell array having plural CMOS static memory cells provided at intersecting portions of plural word lines and plural complementary bit lines. In the memory cell array, a switch MOSFET which is in an OFF state in a first operation mode and in an ON state in a second operation mode different from the first operation mode and first-conductivity-type and second-conductivity-type MOSFETs having a diode configuration are provided in parallel between a first source line to which sources of first-conductivity-type MOSFETs constituting first and second CMOS inverter circuits constituting the plural static memory cells are connected and a first power supply line corresponding to the first source line. A second source line to which sources of the second conductivity-type MOSFETs constituting the first and second CMOS inverter circuits are connected is connected to the second power supply line corresponding thereto.
摘要翻译：本发明的半导体器件具有在多个字线和多个互补位线的交叉部分设置有多个CMOS静态存储单元的存储单元阵列。在存储单元阵列中，开关MOSFET在与第一操作模式不同的第一操作模式和第二操作模式中处于断开状态，并且具有第一导电类型和第二导电类型的MOSFET，其具有在构成构成多个静态存储单元的第一和第二CMOS反相器电路的第一导电型MOSFET的源极连接到的第一源极线和与第一源极线对应的第一电源线之间并联设置二极管配置。构成第一和第二CMOS反相器电路的第二导电型MOSFET的源极连接的第二源极线连接到与其对应的第二电源线。

4. 发明申请

US20060007737A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20060007737A1
公开(公告)日：2006-01-12
申请号：US11224964
申请日：2005-09-14
申请人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
发明人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.
摘要翻译：一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

5. 发明授权

US06930924B2 Nonvolatile memory and method of programming the same memory 有权
标题翻译：非易失性存储器和编程相同存储器的方法
公开(公告)号：US06930924B2
公开(公告)日：2005-08-16
申请号：US10404101
申请日：2003-04-02
申请人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
发明人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12
摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.
摘要翻译：提供了一种编程非易失性存储器的方法，其可以解决现有闪存的数据写入系统的问题，即位线的负载电容变大，位线达到预定电位所需的时间变为因此，数据写入操作所需的时间变得更长，并且由于存储器阵列的存储器电容越多，存储器阵列的长度越长，位线的数量越多，位线的数量越多，因此功耗也变大。在本发明的非易失性存储器中，包括其中多个存储器单元并联连接在局部位线和局部漏极线之间的AND型存储器阵列，通过向局部漏极线提供相对较高的电压来预充电，公共漏极线侧（主位线的相对侧），主位线通过向其施加0V的电压或根据写入数据的相对较小的电压来选择性地预充电，此后，漏极电流仅施加到所选择的通过将写入电压施加到字线来写入数据的存储器单元，以便将热电子注入浮动栅极。

6. 发明申请

US20050047212A1 Nonvolatile semiconductor storage unit 有权
标题翻译：非易失性半导体存储单元
公开(公告)号：US20050047212A1
公开(公告)日：2005-03-03
申请号：US10501391
申请日：2002-02-28
申请人： Michitaro Kanamitsu , Yoshinori Takase , Shoji Kubono
发明人： Michitaro Kanamitsu , Yoshinori Takase , Shoji Kubono
IPC分类号： G11C16/26 , G11C11/34
CPC分类号： G11C16/26
摘要： A nonvolatile semiconductor storage unit can prevent erratic sense operations in a sense latch circuit by adopting a single-end sensing system capable of reducing an area (decreasing the number of elements). There is provided a flash memory chip using the single-end sensing system and an NMOS gate sensing system together. In the single-end sensing system, the sense latch circuit is connected to one end of a global bit line to detect data on the global bit line corresponding to a threshold voltage for a memory cell. The NMOS gate sensing system uses an NMOSFET to receive data on the global bit line at a gate and drive a node for the sense latch circuit. The NMOSFET senses a sense voltage. The sense latch circuit is activated with a sufficient signal quantity ensured. An output voltage from a threshold voltage applying power supply precharges the global bit line. In this manner, it is possible to always keep a constant difference between a precharge voltage and a threshold voltage for the NMOSFET.
摘要翻译：非易失性半导体存储单元可以通过采用能够减小面积（减少元件数量）的单端感测系统来防止感测锁存电路中的错误检测操作。提供了使用单端感测系统和NMOS栅极感测系统的闪存芯片。在单端感测系统中，感测锁存电路连接到全局位线的一端以检测对应于存储器单元的阈值电压的全局位线上的数据。 NMOS栅极感测系统使用NMOSFET在栅极处的全局位线上接收数据，并驱动用于感测锁存电路的节点。 NMOSFET感测感测电压。感测锁存电路在确保足够的信号量的情况下被激活。来自施加电源的阈值电压的输出电压预充电全局位线。以这种方式，可以始终保持NMOSFET的预充电电压和阈值电压之间的恒定差。

7. 发明申请

US20050024948A1 Semiconductor device and data processing system 审中-公开
标题翻译：半导体器件和数据处理系统
公开(公告)号：US20050024948A1
公开(公告)日：2005-02-03
申请号：US10928195
申请日：2004-08-30
申请人： Michitaro Kanamitsu , Yoshinori Takase
发明人： Michitaro Kanamitsu , Yoshinori Takase
IPC分类号： G11C16/02 , G11C11/56 , G11C16/06 , G11C11/34
CPC分类号： G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C2211/5642
摘要： The present invention provides a semiconductor device such as a multi-valued flash memory or the like, which is capable of shortening a processing time required to set write control information to a sense latch. The semiconductor device is capable of electrically writing multi-value information therein. Bit lines are connected to the right and left input/output terminals of a sense latch, and data latches are connected to the respective bit lines. A decoder is provided which decodes write data supplied from outside to thereby generate write control information. The write control information is latched in each of the sense latch and data latches, and the latched control information is set as information indicative of go/no-go of the application of a write voltage, which corresponds to each value in a multivalue. A write operation based on the data latched in the sense latch is first controlled, and the write control information for the sense latches are internally transferred from the data latches in turn subsequently and successively write-controlled.
摘要翻译：本发明提供了诸如多值闪存等的半导体器件，其能够缩短将写入控制信息设置到感测锁存器所需的处理时间。半导体器件能够在其中写入多值信息。位线连接到检测锁存器的右和左输入/输出端子，数据锁存器连接到相应的位线。提供一种解码器，其解码从外部提供的写入数据，从而生成写入控制信息。写入控制信息被锁存在每个读出锁存器和数据锁存器中，并且锁存的控制信息被设置为指示施加写入电压的去/不去的信息，其对应于多值中的每个值。首先控制基于锁存在感测锁存器中的数据的写入操作，并且随后并依次写入控制用于读出锁存器的写入控制信息从数据锁存器进行内部传送。

8. 发明授权

US06233174B1 Non volatile semiconductor, memory 有权
标题翻译：非易失性半导体，存储器
公开(公告)号：US06233174B1
公开(公告)日：2001-05-15
申请号：US09539633
申请日：2000-03-30
申请人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
发明人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
IPC分类号： G11C1134
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/3463 , G11C2211/5642
摘要： A nonvolatile semiconductor memory device having a plurality of memory cells. Each cell stores data and has a threshold voltage corresponding to the data. A controller controls a partial erase operation in response to a command. This operation includes selecting memory cells in two groups, storing the data in a data latch, writing erase data indicating an erase state, erasing data of selected cells and programming the data stored in the data latch to selected memory cells and programming the erased data to selected memory cells.
摘要翻译：一种具有多个存储单元的非易失性半导体存储器件。每个单元存储数据并具有对应于数据的阈值电压。控制器响应命令控制部分擦除操作。该操作包括选择两组中的存储单元，将数据存储在数据锁存器中，写入指示擦除状态的擦除数据，擦除所选单元的数据，并将存储在数据锁存器中的数据编程到所选择的存储单元，并将擦除的数据编程为选定的存储单元。

9. 发明授权

US5311476A Semiconductor memory, components and layout arrangements thereof, and method of testing the memory 失效
公开(公告)号：US5311476A
公开(公告)日：1994-05-10
申请号：US943341
申请日：1992-06-18
申请人： Takeshi Kajimoto , Yutaka Shimbo , Katsuyuki Sato , Masahiro Ogata , Kanehide Kenmizaki , Shouji Kubono , Nobuo Kato , Kiichi Manita , Michitaro Kanamitsu
发明人： Takeshi Kajimoto , Yutaka Shimbo , Katsuyuki Sato , Masahiro Ogata , Kanehide Kenmizaki , Shouji Kubono , Nobuo Kato , Kiichi Manita , Michitaro Kanamitsu
IPC分类号： G01R31/26 , G01R31/28 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/408 , G11C11/409 , G11C11/4093 , G11C29/00 , G11C29/02 , G11C29/14 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H03K3/037 , H03K19/096
CPC分类号： G11C29/027 , G11C11/406 , G11C11/4093 , G11C29/02 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C2029/5004
摘要： There is provided in connection with a semiconductor memory, such as of the pseudostatic RAM, a layout of the circuit components thereof including a method of testing the memory. There is provided an oscillation circuit which is capable of withstanding bumping of the power source voltage (varying) which effects stabilization regarding the operation of the circuits included therewith including a refresh timer circuit. There is also provided for testing a refresh timer circuit and a semiconductor memory which includes a refresh timer circuit. There is further provided for an output buffer which is capable of high speed operation with respect to memory data readout, a voltage generating circuit which is capable of stable operation and a fuse circuit, such as provided in connection with redundant circuitry in the memory and which is characterized as having a configuration of a fuse logic gate circuit employing complementary channel MOSFETs together with a fuse. With respect to the semiconductor memory, such as the pseudostatic RAM, the initial count of the refresh timer counter circuit of the refresh timer circuit can be set at an optional value by applying a signal to an address input terminal, and a test mode can be effected in which the refresh period can be set at an optional value by accordingly applying a test control signal to a predetermined external terminal. Therefore, the discharge current of the oscillation circuit capacitor associated with the refresh timer circuit becomes stabilized, noting the particular layout arrangement regarding the polycrystalline silicon layer forming the resistor of the oscillation circuit, and the fact that same parasitic capacitances are effectively connected between the polycrystalline silicon resistor and the supply voltage of the circuit and between the polycrystalline silicon resistor and the ground potential of the circuit thereby cancelling any variation of the output of the power source. Therefore, variation of the oscillation frequency of the oscillation circuit attributable to the bumping of the power source can be effectively suppressed.

10. 发明授权

US07463533B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07463533B2
公开(公告)日：2008-12-09
申请号：US11605245
申请日：2006-11-29
申请人： Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
发明人： Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
IPC分类号： G11C11/34
CPC分类号： G11C16/3409 , G11C11/5628 , G11C16/0425 , G11C16/0433 , G11C16/0466 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3436 , G11C16/3454 , G11C16/3459 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.
摘要翻译：本发明的非易失性存储器件通过将针对每个编程存储单元设置的特定电容中的电荷累积并且将经过该存储单元的电荷放电时产生的热电子注入到浮动栅极中来执行编程操作。因此，非易失性半导体存储器件的编程特性的变化减小，从而实现高速编程操作。

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