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1. 发明授权

US07463533B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07463533B2
公开(公告)日：2008-12-09
申请号：US11605245
申请日：2006-11-29
申请人： Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
发明人： Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
IPC分类号： G11C11/34
CPC分类号： G11C16/3409 , G11C11/5628 , G11C16/0425 , G11C16/0433 , G11C16/0466 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3436 , G11C16/3454 , G11C16/3459 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.
摘要翻译：本发明的非易失性存储器件通过将针对每个编程存储单元设置的特定电容中的电荷累积并且将经过该存储单元的电荷放电时产生的热电子注入到浮动栅极中来执行编程操作。因此，非易失性半导体存储器件的编程特性的变化减小，从而实现高速编程操作。

2. 发明授权

US07283400B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07283400B2
公开(公告)日：2007-10-16
申请号：US11228389
申请日：2005-09-19
申请人： Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
发明人： Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
IPC分类号： G11C16/04
CPC分类号： G11C16/3409 , G11C11/5628 , G11C16/0425 , G11C16/0433 , G11C16/0466 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3436 , G11C16/3454 , G11C16/3459 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.
摘要翻译：本发明的非易失性存储器件通过将针对每个编程存储单元设置的特定电容中的电荷累积并且将经过该存储单元的电荷放电时产生的热电子注入到浮动栅极中来执行编程操作。因此，非易失性半导体存储器件的编程特性的变化减小，从而实现高速编程操作。

3. 发明申请

US20070076490A1 Nonvolatile semiconductor storage device 有权
公开(公告)号：US20070076490A1
公开(公告)日：2007-04-05
申请号：US11605245
申请日：2006-11-29
申请人： Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
发明人： Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
IPC分类号： G11C16/04
CPC分类号： G11C16/3409 , G11C11/5628 , G11C16/0425 , G11C16/0433 , G11C16/0466 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3436 , G11C16/3454 , G11C16/3459 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.

4. 发明申请

US20060013032A1 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20060013032A1
公开(公告)日：2006-01-19
申请号：US11228389
申请日：2005-09-19
申请人： Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
发明人： Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
IPC分类号： G11C17/00
CPC分类号： G11C16/3409 , G11C11/5628 , G11C16/0425 , G11C16/0433 , G11C16/0466 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3436 , G11C16/3454 , G11C16/3459 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.
摘要翻译：本发明的非易失性存储器件通过将针对每个编程存储单元设置的特定电容中的电荷累积并且将经过该存储单元的电荷放电时产生的热电子注入到浮动栅极中来执行编程操作。因此，非易失性半导体存储器件的编程特性的变化减小，从而实现高速编程操作。

5. 发明授权

US06567315B2 Nonvolatile memory and method of programming the same memory 有权
公开(公告)号：US06567315B2
公开(公告)日：2003-05-20
申请号：US10012549
申请日：2001-12-12
申请人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
发明人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12
摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

6. 发明授权

US06930924B2 Nonvolatile memory and method of programming the same memory 有权
标题翻译：非易失性存储器和编程相同存储器的方法
公开(公告)号：US06930924B2
公开(公告)日：2005-08-16
申请号：US10404101
申请日：2003-04-02
申请人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
发明人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12
摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.
摘要翻译：提供了一种编程非易失性存储器的方法，其可以解决现有闪存的数据写入系统的问题，即位线的负载电容变大，位线达到预定电位所需的时间变为因此，数据写入操作所需的时间变得更长，并且由于存储器阵列的存储器电容越多，存储器阵列的长度越长，位线的数量越多，位线的数量越多，因此功耗也变大。在本发明的非易失性存储器中，包括其中多个存储器单元并联连接在局部位线和局部漏极线之间的AND型存储器阵列，通过向局部漏极线提供相对较高的电压来预充电，公共漏极线侧（主位线的相对侧），主位线通过向其施加0V的电压或根据写入数据的相对较小的电压来选择性地预充电，此后，漏极电流仅施加到所选择的通过将写入电压施加到字线来写入数据的存储器单元，以便将热电子注入浮动栅极。

7. 发明授权

US07072225B2 Nonvolatile memory and method of programming the same memory 失效
公开(公告)号：US07072225B2
公开(公告)日：2006-07-04
申请号：US11168331
申请日：2005-06-29
申请人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
发明人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12
摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

8. 发明申请

US20050237803A1 Nonvolatile memory and method of programming the same memory 失效
公开(公告)号：US20050237803A1
公开(公告)日：2005-10-27
申请号：US11168331
申请日：2005-06-29
申请人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
发明人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12
摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

9. 发明授权

US06285597B1 Semiconductor integrated circuit and data processing system 有权
公开(公告)号：US06285597B1
公开(公告)日：2001-09-04
申请号：US09725011
申请日：2000-11-29
申请人： Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
发明人： Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
IPC分类号： G11C1134
摘要： A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

10. 发明授权

US06459621B1 Semiconductor integrated circuit and data processing system 失效
标题翻译：半导体集成电路和数据处理系统
公开(公告)号：US06459621B1
公开(公告)日：2002-10-01
申请号：US09931030
申请日：2001-08-17
申请人： Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
发明人： Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
IPC分类号： G11C1134
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C29/00 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.
摘要翻译：闪速存储器的控制包括用于向每个非易失性存储单元提供脉冲状电压的控制，直到具有第一阈值电压的非易失性存储单元的阈值电压变为第二阈值电压为止。控制涉及第一写入模式（粗写），其中每当施加脉冲形状电压时变化的每个非易失性存储单元的阈值电压的变化量相对变高，并且第二写入模式（高精度写入），其中阈值电压的变化量相对低。与高精度模式相比，改变每个存储单元的阈值电压所需的脉冲数小于粗写模式时的脉冲数。因此，使用粗写入模式时的验证操作数量很少，因此可以加快整个写入操作。

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