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1. 发明申请

US20070130237A1 Transient cache storage 有权
标题翻译：瞬态缓存存储
公开(公告)号：US20070130237A1
公开(公告)日：2007-06-07
申请号：US11295300
申请日：2005-12-06
申请人： Erik Altman , Michael Gschwind , Robert Montoye , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
发明人： Erik Altman , Michael Gschwind , Robert Montoye , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
IPC分类号： G06F17/30
CPC分类号： G06F12/1491 , G06F9/3808 , G06F9/3844 , G06F12/0802 , G06F12/0804 , G06F12/12
摘要： A method and apparatus for storing non-critical processor information without imposing significant costs on a processor design is disclosed. Transient data are stored in the processor-local cache hierarchy. An additional control bit forms part of cache addresses, where addresses having the control bit set are designated as “transient storage addresses.” Transient storage addresses are not written back to external main memory and, when evicted from the last level of cache, are discarded. Preferably, transient storage addresses are “privileged” in that they are either not accessible to software or only accessible to supervisory or administrator-level software having appropriate permissions. A number of management functions/instructions are provided to allow administrator/supervisor software to manage and/or modify the behavior of transient cache storage. This transient storage scheme allows the cache hierarchy to store data items that may be used by the processor core but that may be too expensive to allocate to external memory.
摘要翻译：公开了一种用于存储非关键处理器信息而不对处理器设计造成重大成本的方法和装置。瞬态数据存储在处理器本地缓存层次结构中。附加控制位构成高速缓存地址的一部分，其中具有控制位置位的地址被指定为“瞬时存储地址”。瞬态存储地址不会被写回外部主存储器，而当从最后一级高速缓存驱逐时，它们将被丢弃。优选地，瞬态存储地址是“特权的”，因为它们不能被软件访问或只能具有具有适当权限的监督或管理员级软件访问。提供了许多管理功能/指令，以允许管理员/管理软件管理和/或修改瞬态缓存存储的行为。这种瞬态存储方案允许高速缓存层级来存储处理器核心可能使用的数据项，但是可能太昂贵以分配给外部存储器。

2. 发明申请

US20060236036A1 Method and apparatus for predictive scheduling of memory accesses based on reference locality 审中-公开
标题翻译：基于参考位置的存储器访问预测调度的方法和装置
公开(公告)号：US20060236036A1
公开(公告)日：2006-10-19
申请号：US11105058
申请日：2005-04-13
申请人： Michael Gschwind , Jude Rivers , John-David Wellman , Victor Zyuban
发明人： Michael Gschwind , Jude Rivers , John-David Wellman , Victor Zyuban
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： There are provided methods and apparatus for accessing a memory array. A method for accessing a memory array includes the step of predicting whether at least two memory references can be satisfied by a single array access based on one of an instruction address, local instruction history and global instruction history.
摘要翻译：提供了用于访问存储器阵列的方法和装置。一种用于访问存储器阵列的方法包括以下步骤：基于指令地址，本地指令历史和全局指令历史中的一个来预测是否可以通过单个阵列访问来满足至少两个存储器引用。

3. 发明申请

US20060174089A1 Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture 审中-公开
标题翻译：用于将宽指令字嵌入固定长度指令集架构中的方法和装置
公开(公告)号：US20060174089A1
公开(公告)日：2006-08-03
申请号：US11047983
申请日：2005-02-01
申请人： Erik Altman , Michael Gschwind , Daniel Prener , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
发明人： Erik Altman , Michael Gschwind , Daniel Prener , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
IPC分类号： G06F15/00
CPC分类号： G06F9/30185 , G06F9/30072 , G06F9/30076 , G06F9/30145 , G06F9/30149 , G06F9/30181 , G06F9/30189 , G06F9/382 , G06F9/3822
摘要： A method, system, and computer program product for mixing of conventional and augmented instructions within an instruction stream, wherein control may be directly transferred, without operating system intervention, between one type of instruction to another. Extra instruction word bits are added in a manner that is designed to minimally interfere with the encoding, decoding, and instruction processing environment in a manner compatible with existing conventional fixed instruction width code. A plurality of instruction words are inserted into an instruction word oriented architecture to form an encoding group of instruction words. The instruction words in the encoding group are dispatched and executed either independently or in parallel based on a specific microprocessor implementation. The encoding group does not indicate any form of required parallelism or sequentiality. One or more indicators for the encoding group are created, wherein one indicator is used to indicate presence of the encoding group.
摘要翻译：一种用于在指令流内混合常规和增强指令的方法，系统和计算机程序产品，其中可以在一种类型的指令与另一种指令之间直接传送控制，而无需操作系统干预。附加指令字位以被设计为以与现有常规固定指令宽度代码兼容的方式最小程度地干扰编码，解码和指令处理环境的方式被添加。多个指令字被插入到面向指令字的架构中以形成指令字的编码组。基于特定的微处理器实现，编码组中的指令字被独立地或并行地调度和执行。编码组不表示任何形式的必需的并行性或顺序性。创建编码组的一个或多个指示符，其中一个指示符用于指示编码组的存在。

4. 发明申请

US20060155965A1 Method and apparatus for control signals memoization in a multiple instruction issue microprocessor 失效
标题翻译：用于在多指令发出微处理器中控制信号记忆的方法和装置
公开(公告)号：US20060155965A1
公开(公告)日：2006-07-13
申请号：US11034284
申请日：2005-01-12
申请人： Erik Altman , Michael Gschwind , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
发明人： Erik Altman , Michael Gschwind , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
IPC分类号： G06F9/30
CPC分类号： G06F9/3808 , G06F9/3838 , G06F9/3859 , G06F9/3873
摘要： A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.
摘要翻译：在微处理器管线的各个阶段提供动态预测和/或精确缓存机制，使得可以在程序执行过程中存储和存储各种控制信号。精确的控制信号矢量缓存可以完成。每当在指令解码，注册重命名和依赖关系检查之后形成问题组时，可以在引导指令的标签下缓存问题组信息的编码副本。所产生的依赖性高速缓存或控制向量高速缓存可以在微处理器流水线的指令发出逻辑阶段的开始时被下一次相应的指令组出现以重新执行。由于可以在高速缓存中的单个周期中访问编码的问题组位模式，所以具有该实施例的所得微处理器流水线可以被看作是两个并行的管道，其中如果存在依赖性高速缓存或控制向量高速缓存击中。

5. 发明申请

US20080052495A1 SYSTEM AND METHOD OF EXECUTION OF REGISTER POINTER INSTRUCTIONS AHEAD OF INSTRUCTION ISSUES 有权
标题翻译：注册指示器的指导性问题的执行系统及方法
公开(公告)号：US20080052495A1
公开(公告)日：2008-02-28
申请号：US11924977
申请日：2007-10-26
申请人： ERIK ALTMAN , Michael Gschwind , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
发明人： ERIK ALTMAN , Michael Gschwind , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30036 , G06F9/3013 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F9/3885
摘要： A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.
摘要翻译：管道系统和方法包括多个操作阶段。这些阶段包括存储指针信息和更新的指针寄存器阶段，以及位于指针寄存器阶段下游的重命名和依赖性检查阶段，其重新命名寄存器并确定是否存在相关性。功能单元向指针寄存器阶段提供指针信息更新，使得指针信息在寄存器依赖性检查之前或与寄存器依赖性检查并行地更新到指针寄存器阶段。

6. 发明申请

US20070162895A1 Mechanism and method for two level adaptive trace prediction 审中-公开
标题翻译：二级自适应跟踪预测的机理与方法
公开(公告)号：US20070162895A1
公开(公告)日：2007-07-12
申请号：US11329319
申请日：2006-01-10
申请人： Erik Altman , Michael Gschwind , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
发明人： Erik Altman , Michael Gschwind , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
IPC分类号： G06F9/44
CPC分类号： G06F9/3808 , G06F9/3844
摘要： A trace cache system is provided comprising a trace start address cache for storing trace start addresses with successor trace start addresses, a trace cache for storing traces of instructions executed, a trace history table (THT) for storing trace numbers in rows, a branch history shift register (BHSR) or a trace history shift register (THSR) that stores histories of branches or traces executed, respectively, a THT row selector for selecting a trace number row from the THT, the selection derived from a combination of a trace start address and history information from the BHSR or the THSR, and a trace number selector for selecting a trace number from the selected trace number row and for outputting the selected trace number as a predicted trace number.
摘要翻译：提供了一种跟踪缓存系统，包括用于存储具有后续跟踪开始地址的跟踪起始地址的跟踪起始地址缓存，用于存储所执行的指令轨迹的跟踪高速缓存，用于存储行中的跟踪数的跟踪历史表（THT），分支历史移位寄存器（BHSR）或跟踪历史移位寄存器（THSR），其分别存储执行的分支或跟踪的历史，THT行选择器，用于从THT中选择跟踪号行，该选择是从跟踪起始地址和来自BHSR或THSR的历史信息，以及轨迹号选择器，用于从所选轨迹号行中选择一个轨迹号，并输出所选轨迹号作为预测轨迹号。

7. 发明申请

US20050251654A1 System and method of execution of register pointer instructions ahead of instruction issue 有权
标题翻译：提前执行寄存器指针指令的系统和方法问题
公开(公告)号：US20050251654A1
公开(公告)日：2005-11-10
申请号：US10828794
申请日：2004-04-21
申请人： Erik Altman , Michael Gschwind , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
发明人： Erik Altman , Michael Gschwind , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/30036 , G06F9/3013 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F9/3885
摘要： A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.
摘要翻译：管道系统和方法包括多个操作阶段。这些阶段包括存储指针信息和更新的指针寄存器阶段，以及位于指针寄存器阶段下游的重命名和依赖性检查阶段，其重新命名寄存器并确定是否存在相关性。功能单元向指针寄存器阶段提供指针信息更新，使得指针信息在寄存器依赖性检查之前或与寄存器依赖性检查并行地更新到指针寄存器阶段。

8. 发明申请

US20080065861A1 Method And Apparatus To Extend The Number Of Instruction Bits In Processors With Fixed Length Instructions, In A Manner Compatible With Existing Code 有权
标题翻译：使用固定长度指令扩展处理器中指令位数的方法和装置，与现有代码兼容
公开(公告)号：US20080065861A1
公开(公告)日：2008-03-13
申请号：US11931815
申请日：2007-10-31
申请人： Erik Altman , Michael Gschwind , David Luick , Daniel Prener , Jude Rivers , Sumedh Sathaye , John-David Wellman
发明人： Erik Altman , Michael Gschwind , David Luick , Daniel Prener , Jude Rivers , Sumedh Sathaye , John-David Wellman
IPC分类号： G06F9/30
CPC分类号： G06F9/3816 , G06F9/30149 , G06F9/30181 , G06F9/30185
摘要： This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.
摘要翻译：本发明涉及存储在计算机可读介质上的装置，方法和计算机程序。计算机程序包括与具有代码页的指令单元一起使用的指令，并且具有用于将代码页划分为至少两个部分的计算机程序代码，用于在其第一部分中存储多个指令字，并且至少与一个指令字，用于在其第二部分中存储对第一部分中的每个指令字的扩展。计算机程序还包括用于设置至少一个页表条目位的状态的计算机程序代码，用于通过代码页在代码页上指示代码页是否被分割成用于存储指令字的第一和第二部分，以及它们扩展，还是包含代码页而不是仅存储指令字的单个部分。

9. 发明申请

US20050114629A1 Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code 有权
标题翻译：以与现有代码兼容的方式扩展具有固定长度指令的处理器中指令位数目的方法和装置
公开(公告)号：US20050114629A1
公开(公告)日：2005-05-26
申请号：US10720585
申请日：2003-11-24
申请人： Erik Altman , Michael Gschwind , David Luick , Daniel Prener , Jude Rivers , Sumedh Sathaye , John-David Wellman
发明人： Erik Altman , Michael Gschwind , David Luick , Daniel Prener , Jude Rivers , Sumedh Sathaye , John-David Wellman
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3816 , G06F9/30149 , G06F9/30181 , G06F9/30185
摘要： This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.
摘要翻译：本发明涉及存储在计算机可读介质上的装置，方法和计算机程序。计算机程序包括与具有代码页的指令单元一起使用的指令，并且具有用于将代码页划分为至少两个部分的计算机程序代码，用于在其第一部分中存储多个指令字，并且至少与一个指令字，用于在其第二部分中存储对第一部分中的每个指令字的扩展。计算机程序还包括用于设置至少一个页表条目位的状态的计算机程序代码，用于通过代码页在代码页上指示代码页是否被分割成用于存储指令字的第一和第二部分，以及它们扩展，还是包含代码页而不是仅存储指令字的单个部分。

10. 发明申请

US20080168260A1 Symbolic Execution of Instructions on In-Order Processors 审中-公开
标题翻译：符号执行有序处理器的说明
公开(公告)号：US20080168260A1
公开(公告)日：2008-07-10
申请号：US11620790
申请日：2007-01-08
申请人： Victor Zyuban , Michael K. Gschwind , John-David Wellman
发明人： Victor Zyuban , Michael K. Gschwind , John-David Wellman
IPC分类号： G06F9/312
CPC分类号： G06F9/3851 , G06F9/3838 , G06F9/3842
摘要： A method is provided for processing instructions by a processor, in which instructions are queued in an instruction pipeline in a queued order. A first instruction is identified from the queued instructions in the instruction pipeline, the first instruction being identified as having a dependency which is satisfiable within a number of instruction cycles after a current instruction in the instruction pipeline is issued. The first instruction is placed in a side buffer and at least one second instruction is issued from the remaining queued instructions while the first instruction remains in the side buffer. Then, the first instruction is issued from the side buffer after issuing the at least one second instruction in the queued order when the dependency of the first instruction has cleared and after the number of instruction cycles have passed.
摘要翻译：提供了一种处理器处理指令的方法，其中指令以排队的顺序排队在指令流水线中。从指令流水线中的排队指令中识别第一指令，第一指令被识别为在发出指令流水线中的当前指令之后的多个指令周期内具有可满足的依赖性。第一指令被放置在边缓冲器中，并且当第一指令保留在边缓冲器中时，从剩余的排队指令发出至少一个第二指令。然后，当第一指令的相关性已经清除并且在指令周期数已经过去之后，以排队顺序发出至少一个第二指令之后，从侧缓冲器发出第一指令。

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