专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06546453B1 Proprammable DRAM address mapping mechanism 失效
标题翻译：可预测的DRAM地址映射机制
公开(公告)号：US06546453B1
公开(公告)日：2003-04-08
申请号：US09653093
申请日：2000-08-31
申请人： Richard E. Kessler , Maurice B. Steinman , Peter J. Bannon , Michael C. Braganza , Gregg A. Bouchard
发明人： Richard E. Kessler , Maurice B. Steinman , Peter J. Bannon , Michael C. Braganza , Gregg A. Bouchard
IPC分类号： G06F1200
CPC分类号： G06F12/0882 , G06F12/0215 , G06F12/0607
摘要： A computer system contains a processor that includes a software programmable memory mapper. The memory mapper maps an address generated by the processor into a device address for accessing physical main memory. The processor also includes a cache controller that maps the processor address into a cache address. The cache address places a block of data from main memory into a memory cache using an index subfield. The physical main memory contains RDRAM devices, each of the RDRAM devices containing a number of memory banks that store rows and columns of data. The memory mapper maps processor addresses to device addresses to increases memory system performance. The mapping minimizes memory access conflicts between the memory banks. Conflicts between memory banks are reduced by placing a number of bits corresponding to the bank subfield above the most significant boundary bit of the index subfield. This diminishes page misses caused by replacement of data blocks from the cache memory because the read of the new data block and write of the victim data block are not to the same memory bank. Adjacent memory bank conflicts are reduced for sequential accesses to memory banks by reversing the bit order of a bank number subfield within the bank subfield of the device address.
摘要翻译：计算机系统包含包括软件可编程存储器映射器的处理器。存储器映射器将由处理器生成的地址映射到用于访问物理主存储器的设备地址。处理器还包括将处理器地址映射到高速缓存地址的高速缓存控制器。高速缓存地址使用索引子字段将主存储器的数据块放入存储器高速缓存。物理主存储器包含RDRAM设备，每个RDRAM设备包含存储行和数据列的多个存储器组。内存映射器将处理器地址映射到设备地址，以提高内存系统性能。该映射最小化了存储体之间的存储器访问冲突。通过将对应于银行子字段的多个位放置在索引子字段的最高有效边界位之上来减少存储体之间的冲突。由于新数据块的读取和受害者数据块的写入不是同一个存储体，这会减少由高速缓冲存储器替换数据块所造成的页面错误。通过反转设备地址的银行子字段内的库号子字段的位顺序，减少了对存储体的顺序访问的相邻存储体冲突。

2. 发明授权

US06622225B1 System for minimizing memory bank conflicts in a computer system 有权
标题翻译：用于最小化计算机系统中的存储器组冲突的系统
公开(公告)号：US06622225B1
公开(公告)日：2003-09-16
申请号：US09652325
申请日：2000-08-31
申请人： Richard E. Kessler , Michael S. Bertone , Michael C. Braganza , Gregg A. Bouchard , Maurice B. Steinman
发明人： Richard E. Kessler , Michael S. Bertone , Michael C. Braganza , Gregg A. Bouchard , Maurice B. Steinman
IPC分类号： G06F1200
CPC分类号： G06F13/1642
摘要： A computer system includes a memory controller interfacing the processor to a memory system. The memory controller supports a memory system with a plurality of memory devices, with multiple memory banks in each memory device. The memory controller supports simultaneous memory accesses to different memory banks. Memory bank conflicts are avoided by examining each transaction before it is loaded in the memory transaction queue. On a first clock cycle, the new pending memory request is transferred from a pending request queue to a memory mapper. On the subsequent clock cycle, the memory mapper formats the pending memory request into separate signals identifying the DEVICE, BANK, ROW and COLUMN to be accessed by the pending transaction. In the next clock cycle, the DEVICE and BANK signals are compared with every entry in the memory transaction queue to determine if a bank conflict exists. If so, the new memory request is rejected and recycled to the pending request queue.
摘要翻译：计算机系统包括将处理器与存储器系统接口的存储器控制器。存储器控制器支持具有多个存储器设备的存储器系统，每个存储器设备中具有多个存储体。存储器控制器支持对不同存储体的同时存储器访问。通过在每个事务加载到内存事务队列中之前检查每个事务来避免存储器组冲突。在第一个时钟周期中，新的挂起的存储器请求从挂起的请求队列传送到存储器映射器。在随后的时钟周期中，存储器映射器将待处理的存储器请求格式化成单独的信号，标识要由待处理事务访问的DEVICE，BANK，ROW和COLUMN。在下一个时钟周期中，将DEVICE和BANK信号与存储器事务队列中的每个条目进行比较，以确定是否存在存储库冲突。如果是这样，新的内存请求被拒绝并被回收到挂起的请求队列。

3. 发明授权

US07024533B2 Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature 失效
公开(公告)号：US07024533B2
公开(公告)日：2006-04-04
申请号：US10441451
申请日：2003-05-20
申请人： Richard E. Kessler , Peter J. Bannon , Maurice B. Steinman , Scott E. Breach , Allen J. Baum , Gregg A. Bouchard
发明人： Richard E. Kessler , Peter J. Bannon , Maurice B. Steinman , Scott E. Breach , Allen J. Baum , Gregg A. Bouchard
IPC分类号： G06F12/00
CPC分类号： G06F13/1689
摘要： A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.

4. 发明授权

US06636955B1 Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature 失效
标题翻译：同步多个偏斜源同步数据通道与自动初始化功能的机制
公开(公告)号：US06636955B1
公开(公告)日：2003-10-21
申请号：US09652480
申请日：2000-08-31
申请人： Richard E. Kessler , Peter J. Bannon , Maurice B. Steinman , Scott E. Breach , Allen J. Baum , Gregg A. Bouchard
发明人： Richard E. Kessler , Peter J. Bannon , Maurice B. Steinman , Scott E. Breach , Allen J. Baum , Gregg A. Bouchard
IPC分类号： G06F1200
CPC分类号： G06F13/1689
摘要： A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself. Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.
摘要翻译：计算机系统具有存储器控制器，其包括耦合到多个存储器通道的读取缓冲器。存储器控制器有利地消除由存储器模块位于与存储器控制器不同的距离处引起的通道间偏移。存储器控制器优选地包括用于每个存储器通道的通道接口和同步逻辑电路。该电路包括读取和写入缓冲区，读取缓冲区的加载和卸载指针。卸载指针逻辑生成卸载指针，加载指针逻辑生成加载指针。指针优选地是根据两个不同的时钟信号递增的自由运行指针。负载指针根据由存储器控制器产生的时钟增加，但是已经被引出到存储器模块和从存储器模块返回。卸载指针根据计算机系统本身产生的时钟增加。因为每个存储器通道的迹线长度可能不同，所以存储器模块将读数据提供给存储器控制器所花费的时间可能对于每个通道而言可能不同。 “偏斜”被定义为数据到达最早通道时和数据到达最新通道之间的时间差。在系统初始化期间，指针是同步的。初始化之后，这些指针用于加载和卸载读取缓冲区，从而消除内部信道偏移的影响。

5. 发明授权

US06662265B1 Mechanism to track all open pages in a DRAM memory system 有权
标题翻译：跟踪DRAM存储器系统中所有打开的页面的机制
公开(公告)号：US06662265B1
公开(公告)日：2003-12-09
申请号：US09652704
申请日：2000-08-31
申请人： Richard E. Kessler , Maurice B. Steinman , Michael S. Bertone , Peter J. Bannon , Gregg A. Bouchard
发明人： Richard E. Kessler , Maurice B. Steinman , Michael S. Bertone , Peter J. Bannon , Gregg A. Bouchard
IPC分类号： G06F1200
CPC分类号： G06F12/0215 , G06F13/1631
摘要： A system and method is disclosed to track a large number of open pages in a computer memory system. The computer system contains one or more processors each including a memory controller containing a page table, the page table organized into a plurality of rows with each row able to store an address of an open memory page. A RIMM module containing RDRAM devices is coupled to each processor, each RDRAM containing a plurality of memory banks. The page table increases system memory performance by tracking a large number of open memory pages. Associated with the page table is a bank active table that indicates the memory banks in each RDRAM device having open memory pages. The page table enqueues accesses to the RIMM module in a precharge queue resulting from a page miss caused by the address of an open memory page occupying the same row of the page table as the address of the system memory access resulting in the page miss. The page table also enqueues accesses to system memory in a Row-address-select (“RAS”) queue resulting from a page miss caused by a row of the page table not containing any open memory page address. The page table enqueues accesses to system memory resulting in page hits to open memory pages in a Column-address-select (“CAS”) queue. An entry in the precharge queue is then enqueued into the RAS queue. An entry in the RAS queue after completion is enqueued into the CAS Read or CAS Write queue.
摘要翻译：公开了一种在计算机存储器系统中跟踪大量打开页面的系统和方法。计算机系统包含一个或多个处理器，每个处理器包括包含页表的存储器控制器，所述页表被组织成多行，每行能够存储打开存储器页的地址。包含RDRAM设备的RIMM模块耦合到每个处理器，每个RDRAM包含多个存储器组。页面表通过跟踪大量的开放内存页面来增加系统内存性能。与页表相关联的是一个存储区活动表，指示每个具有打开存储器页的RDRAM设备中的存储体。页表格排队访问预充电队列中的RIMM模块，这是由于打开的内存页面的地址与页表的同一行的地址导致的页错误导致的系统内存访问的地址导致页错过。页表还对由行页地址选择（“RAS”）队列访问系统内存进行排队，这是由于不包含任何打开的内存页地址的页表的行引起的页错误导致的。页面表格对对系统内存的访问进行排队，导致页面命中，以打开列地址选择（“CAS”）队列中的内存页面。然后将预充电队列中的条目排入RAS队列。完成后RAS队列中的条目排入CAS读取或CAS写入队列。

6. 发明授权

US06754739B1 Computer resource management and allocation system 有权
标题翻译：计算机资源管理与分配系统
公开(公告)号：US06754739B1
公开(公告)日：2004-06-22
申请号：US09651945
申请日：2000-08-31
申请人： Richard E. Kessler , Michael S. Bertone , Gregg A. Bouchard , Maurice B. Steinman
发明人： Richard E. Kessler , Michael S. Bertone , Gregg A. Bouchard , Maurice B. Steinman
IPC分类号： G06F1300
CPC分类号： G06F9/544
摘要： A method and architecture for improved system resource management and allocation for the processing of request and response messages in a computer system. The resource management scheme provides for dynamically sharing system resources, such as data buffers, between request and response messages or transactions. In particular, instead of simply dedicating a portion of the system resources to requests and the remaining portion to responses, a minimum amount of resources are reserved for responses and a minimum amount for requests, while the remaining resources are dynamically shared between both types of messages. The method and architecture of the present invention allows for more efficient use of system resources, while avoiding deadlock conditions and ensuring a minimum service rate for requests.
摘要翻译：一种用于改进系统资源管理和分配以在计算机系统中处理请求和响应消息的方法和架构。资源管理方案提供在请求和响应消息或事务之间动态共享系统资源，例如数据缓冲器。特别地，不是简单地将系统资源的一部分专用于请求，而将余下的部分用于响应，而是为响应保留最小量的资源和用于请求的最小量，而剩余的资源在两种类型的消息之间动态共享。本发明的方法和体系结构允许更有效地利用系统资源，同时避免死锁状况并确保请求的最低服务速率。

7. 发明授权

US06920512B2 Computer architecture and system for efficient management of bi-directional bus 有权
标题翻译：用于双向总线高效管理的计算机架构和系统
公开(公告)号：US06920512B2
公开(公告)日：2005-07-19
申请号：US10780395
申请日：2004-02-17
申请人： Maurice B. Steinman , Richard E. Kessler , Gregg A. Bouchard
发明人： Maurice B. Steinman , Richard E. Kessler , Gregg A. Bouchard
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4059
摘要： An efficient system and method for managing reads and writes on a bi-directional bus to optimize bus performance while avoiding bus contention and avoiding read/write starvation. In particular, by intelligently managing reads and writes on a bi-directional bus, bus latency can be reduced while still ensuring no bus contention or read/write starvation. This is accomplished by utilizing bus streaming control logic, separate queues for reads and writes, and a simple 2 to 1 mux.
摘要翻译：一种有效的系统和方法，用于管理双向总线上的读取和写入，以优化总线性能，同时避免总线争用并避免读取/写入饥饿。特别地，通过智能地管理双向总线上的读取和写入，可以减少总线延迟，同时仍然确保没有总线争用或读取/写入饥饿。这是通过利用总线流控制逻辑，单独的队列读取和写入以及简单的2到1多路复用来实现的。

8. 发明授权

US06704817B1 Computer architecture and system for efficient management of bi-directional bus 有权
标题翻译：用于双向总线高效管理的计算机架构和系统
公开(公告)号：US06704817B1
公开(公告)日：2004-03-09
申请号：US09652323
申请日：2000-08-31
申请人： Maurice B. Steinman , Richard E. Kessler , Gregg A. Bouchard
发明人： Maurice B. Steinman , Richard E. Kessler , Gregg A. Bouchard
IPC分类号： G06F1300
CPC分类号： G06F13/4059
摘要： An efficient system and method for managing reads and writes on a bi-directional bus to optimize bus performance while avoiding bus contention and avoiding read/write starvation. In particular by intelligently managing reads and writes on a bi-directional bus, bus latency can be reduced while still ensuring no bus contention or read/write starvation. This is accomplished by utilizing bus streaming control logic, separate queues for reads and writes, and a simple 2 to 1 mux.
摘要翻译：一种有效的系统和方法，用于管理双向总线上的读取和写入，以优化总线性能，同时避免总线争用并避免读取/写入饥饿。特别是通过智能地管理双向总线上的读写操作，可以减少总线延迟，同时确保没有总线争用或读/写饥饿。这是通过利用总线流控制逻辑，单独的队列读取和写入以及简单的2到1多路复用来实现的。

9. 发明授权

US08850125B2 System and method to provide non-coherent access to a coherent memory system 有权
标题翻译：提供对相干存储器系统的非相干访问的系统和方法
公开(公告)号：US08850125B2
公开(公告)日：2014-09-30
申请号：US13280756
申请日：2011-10-25
申请人： Jeffrey Pangborn , Gregg A. Bouchard , Rajan Goyal , Richard E. Kessler , Aseem Maheshwari
发明人： Jeffrey Pangborn , Gregg A. Bouchard , Rajan Goyal , Richard E. Kessler , Aseem Maheshwari
IPC分类号： G06F13/00 , G06F13/28 , G06F12/08
CPC分类号： G06F12/0888 , G06F12/08 , G06F12/0831
摘要： In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
摘要翻译：在一个实施例中，系统包括存储器和存储器控制器，其提供到存储器的高速缓存访问路径和到存储器的旁路高速缓存访问路径，接收从旁路高速缓存访问路径上的存储器读取图形数据的请求，以及接收从缓存访问路径上的内存中读取非图形数据的请求。一种方法包括在存储器控制器处接收来自旁路高速缓存访问路径上的存储器的图形数据的请求，在存储器控制器处接收请求以通过高速缓存访问路径从存储器读取非图形数据，在内存控制器中，在使用仲裁的请求中。

10. 发明授权

US07594081B2 Direct access to low-latency memory 有权
标题翻译：直接访问低延迟内存
公开(公告)号：US07594081B2
公开(公告)日：2009-09-22
申请号：US11024002
申请日：2004-12-28
申请人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler , Muhammad R. Hussain
发明人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler , Muhammad R. Hussain
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/3824 , G06F9/3885 , G06F12/0888
摘要： A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.
摘要翻译：提供内容感知应用处理系统，用于允许定向访问存储在非高速缓冲存储器中的数据，从而绕过高速缓存一致存储器。该处理器包括用于缓存相干存储器的系统接口和用于非高速缓存一致记忆体的低延迟存储器接口。系统接口将由处理器执行的普通加载/存储指令的存储器访问指向高速缓存一致存储器。低延迟存储器接口将由处理器执行的非普通加载/存储指令的存储器访问引导到非高速缓存存储器，从而绕过高速缓存一致存储器。非普通的加载/存储指令可以是协处理器指令。存储器可以是低延迟型存储器。处理器可以包括多个处理器核。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式