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1. 发明授权

US06714464B2 System and method for a self-calibrating sense-amplifier strobe 有权
标题翻译：用于自校准读出放大器选通的系统和方法
公开(公告)号：US06714464B2
公开(公告)日：2004-03-30
申请号：US10180478
申请日：2002-06-26
申请人： Ajay Bhatia , Michael C. Braganza , Shannon V. Morton , Shashank Shastry
发明人： Ajay Bhatia , Michael C. Braganza , Shannon V. Morton , Shashank Shastry
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/06 , G11C7/22 , G11C2207/065 , G11C2207/2254
摘要： A system and method for self-calibration of the strobe timing of the sense-amplifiers of a RAM array. In one method example, the timing of two sense amplifiers used to read the bit-lines of the RAM array is controlled by a Delay Locked Loop circuit (DLL). The timing of a first sense-amplifier strobe is reduced until the sense amplifier fails. The second sense amplifier has adequate timing margin however and is used to actually read the RAM bit-lines. Once the RAM read fails with the first sense amplifier, the DLL lengthens the strobe timing. Once the minimum threshold is set, the second sense amplifier will always read the correct data because of a built-in timing margin between the first and second amplifier. Thus the system constantly optimizes the RAM array read timing with each read cycle even though the minimal time varies.
摘要翻译：用于RAM阵列的读出放大器的选通定时的自校准的系统和方法。在一个方法示例中，用于读取RAM阵列的位线的两个读出放大器的定时由延迟锁定环电路（DLL）控制。第一感测放大器选通脉冲的定时降低，直到读出放大器发生故障。然而，第二感测放大器具有足够的定时裕度，并用于实际读取RAM位线。一旦RAM读取失败，第一个读出放大器，DLL会延长选通时序。一旦设置了最小阈值，由于第一和第二放大器之间的内置定时裕度，第二读出放大器将始终读取正确的数据。因此，即使最小时间变化，系统也会随着每个读取周期不断优化RAM阵列读取定时。

2. 发明授权

US07474546B2 Hybrid dual match line architecture for content addressable memories and other data structures 失效
标题翻译：用于内容可寻址存储器和其他数据结构的混合双匹配线架构
公开(公告)号：US07474546B2
公开(公告)日：2009-01-06
申请号：US11695395
申请日：2007-04-02
申请人： Shashank Shastry , Sagar V. Reddy , Ajay Bhatia
发明人： Shashank Shastry , Sagar V. Reddy , Ajay Bhatia
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G06F7/02 , G06F12/0895 , G06F12/1027
摘要： A hybrid dual match line circuit may include a hit match line coupled to a first group of load devices and a miss match line coupled to discharge through a second group of load devices. Both the hit and miss match lines may be configured to be precharged to an asserted state. Each of the second group of load devices may be activated for discharging by a respective miss signal. The hit match line may be additionally coupled to discharge through first and second discharge path respectively activated for discharging in response to a hit signal and a read/write enable signal. The hit and miss match lines may be electrically isolated from one another, such that when one or more of the respective miss signals are asserted, current from the hit match line does not discharge through the miss match line.
摘要翻译：混合双匹配线路电路可以包括耦合到第一组负载装置的匹配匹配线和耦合到通过第二组负载装置放电的未匹配线。命中和未命中匹配线都可以被配置为预充电到断言状态。可以通过相应的未命中信号来激活第二组负载装置中的每一个以进行放电。命中匹配线可以另外耦合到通过响应于命中信号和读/写使能信号分别被激活以用于放电的第一和第二放电路径放电。命中和未命中匹配线可以彼此电隔离，使得当相应的未命中信号中的一个或多个被断言时，来自命中匹配线的电流不会通过未命中匹配线放电。

3. 发明授权

US07200019B1 Dual match line architecture for content addressable memories and other data structures 有权
标题翻译：双匹配线架构，用于内容可寻址存储器和其他数据结构
公开(公告)号：US07200019B1
公开(公告)日：2007-04-03
申请号：US11141301
申请日：2005-05-31
申请人： Ajay Bhatia , Sanjay M. Wanzakhade , Shashank Shastry
发明人： Ajay Bhatia , Sanjay M. Wanzakhade , Shashank Shastry
IPC分类号： G11C15/04 , G06F12/00
CPC分类号： G11C15/04 , G06F12/1009 , Y02D10/13
摘要： A dual match line circuit may include precharge logic configured to precharge each of a hit match line, a miss match line and an evaluate node to an asserted state, where a coupling device couples the hit and miss match lines to the evaluate node. The miss match line may discharge through a number of load devices that may be activated by respective miss signals. The hit match line may be additionally coupled to discharge through a pair of devices connected in series, one of which may be activated by a hit signal, and the other of which may be activated by the miss match line. The hit and miss match lines may be electrically isolated from one another, such that when any of the respective miss signals is asserted, current from the hit match line does not discharge through the miss match line.
摘要翻译：双匹配线路电路可以包括预充电逻辑，其被配置为将命中匹配线，未命中匹配线和评估节点中的每一个预先充电到断言状态，其中耦合设备将命中和未命中匹配线耦合到评估节点。错过匹配线可以通过可能由相应的未命中信号激活的多个负载装置放电。命中匹配线可以另外耦合以通过串联连接的一对装置放电，其中一个可以由命中信号激活，并且另一个可以由未匹配线激活。命中和未命中匹配线可以彼此电隔离，使得当相应的未命中信号中的任一个被断言时，来自命中匹配线的电流不会通过未命中匹配线放电。

4. 发明申请

US20080239778A1 HYBRID DUAL MATCH LINE ARCHITECTURE FOR CONTENT ADDRESSABLE MEMORIES AND OTHER DATA STRUCTURES 失效
标题翻译：用于内容可寻址存储器和其他数据结构的混合双匹配线架构
公开(公告)号：US20080239778A1
公开(公告)日：2008-10-02
申请号：US11695395
申请日：2007-04-02
申请人： Shashank Shastry , Sagar V. Reddy , Ajay Bhatia
发明人： Shashank Shastry , Sagar V. Reddy , Ajay Bhatia
IPC分类号： G11C15/04 , G06F12/02 , G11C15/00
CPC分类号： G11C15/04 , G06F7/02 , G06F12/0895 , G06F12/1027
摘要： A hybrid dual match line circuit may include a hit match line coupled to a first group of load devices and a miss match line coupled to discharge through a second group of load devices. Both the hit and miss match lines may be configured to be precharged to an asserted state. Each of the second group of load devices may be activated for discharging by a respective miss signal. The hit match line may be additionally coupled to discharge through first and second discharge path respectively activated for discharging in response to a hit signal and a read/write enable signal. The hit and miss match lines may be electrically isolated from one another, such that when one or more of the respective miss signals are asserted, current from the hit match line does not discharge through the miss match line.
摘要翻译：混合双匹配线路电路可以包括耦合到第一组负载装置的匹配匹配线和耦合到通过第二组负载装置放电的未匹配线。命中和未命中匹配线都可以被配置为预充电到断言状态。可以通过相应的未命中信号来激活第二组负载装置中的每一个以进行放电。命中匹配线可以另外耦合到通过响应于命中信号和读/写使能信号分别被激活以用于放电的第一和第二放电路径放电。命中和未命中匹配线可以彼此电隔离，使得当相应的未命中信号中的一个或多个被断言时，来自命中匹配线的电流不会通过未命中匹配线放电。

5. 发明授权

US07203082B1 Race condition improvements in dual match line architectures 有权
标题翻译：双匹配线路架构中的竞争状况改善
公开(公告)号：US07203082B1
公开(公告)日：2007-04-10
申请号：US11144123
申请日：2005-05-31
申请人： Ajay Bhatia , Sanjay M. Wanzakhade , Shashank Shastry
发明人： Ajay Bhatia , Sanjay M. Wanzakhade , Shashank Shastry
IPC分类号： G11C15/04 , G06F12/00
CPC分类号： G11C15/04 , G06F12/0895 , G06F12/1027 , Y02D10/13
摘要： Dual match line circuits having race condition improvements. A dual match line circuit may include precharge logic configured to precharge each of a hit match line, a miss match line and an evaluate node to an asserted state, where a coupling device couples the hit and miss match lines to the evaluate node. The miss match line may discharge through a number of load devices that may be activated by respective miss signals. A positive feedback circuit coupled to the miss match line may accelerate its discharge. The hit match line may be additionally coupled to discharge through a discharge path. The hit and miss match lines may be electrically isolated from one another, such that when any of the respective miss signals is asserted, current from the hit match line does not discharge through the miss match line.
摘要翻译：具有竞争条件改进的双匹配线路电路。双匹配线路电路可以包括预充电逻辑，其被配置为将命中匹配线，未命中匹配线和评估节点中的每一个预先充电到断言状态，其中耦合设备将命中和未命中匹配线耦合到评估节点。错过匹配线可以通过可能由相应的未命中信号激活的多个负载装置放电。耦合到未匹配线的正反馈电路可以加速其放电。命中匹配线可以另外耦合以通过放电路径放电。命中和未命中匹配线可以彼此电隔离，使得当相应的未命中信号中的任一个被断言时，来自命中匹配线的电流不会通过未命中匹配线放电。

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