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1. 发明授权

US06317879B1 Method and apparatus for synchronizing distributed computer systems 失效
标题翻译：用于同步分布式计算机系统的方法和设备
公开(公告)号：US06317879B1
公开(公告)日：2001-11-13
申请号：US08988948
申请日：1997-12-11
申请人： James E. Jacobson, Jr. , David E. Dent
发明人： James E. Jacobson, Jr. , David E. Dent
IPC分类号： G06F9445
CPC分类号： G06F11/0709 , G06F9/4416 , G06F11/0793 , G06F11/1433 , G06F11/3006 , G06F11/3055 , G06F11/3089
摘要： An apparatus for use in a member hardware system of a distributed collection of hardware systems includes monitor logic that cooperates with like logic of the other hardware systems to collectively monitor wellness of all hardware systems of the distributed collection of hardware systems and determine whether the hardware systems should be re-synchronized. The apparatus also includes reset logic communicatively coupled with the monitor logic that resets the member hardware system and causes the member hardware system to be rebooted off a common system image disposed in a boot one of the distributed collection of hardware systems, responsive to the monitor logic determining the hardware systems should be re-synchronized.
摘要翻译：用于硬件系统的分布式集合的成员硬件系统中的装置包括与其他硬件系统的类似逻辑配合的监视逻辑，以共同监视硬件系统的分布式集合的所有硬件系统的健康状况，并确定硬件系统应该重新同步该装置还包括与监视器逻辑通信耦合的复位逻辑，其复位成员硬件系统，并使得成员硬件系统响应于监视逻辑而被布置在分布式硬件系统集合中的引导中的公共系统映像上重新启动确定硬件系统应该重新同步。

2. 发明授权

US4414623A Dual deadman timer circuit 失效
标题翻译：双重死机定时器电路
公开(公告)号：US4414623A
公开(公告)日：1983-11-08
申请号：US192772
申请日：1980-10-01
申请人： Walter L. Davis , James E. Jacobson, Jr.
发明人： Walter L. Davis , James E. Jacobson, Jr.
IPC分类号： G06F1/00 , G06F1/24 , G06F1/32 , G06F9/00 , G06F11/00 , G06F11/14 , G06F11/30 , H04Q7/14 , G06F1/04
CPC分类号： G06F11/0757 , G06F11/1415
摘要： A dual deadman timer circuit functions to reset a dual mode microprocessor in the event of loss of program control. The microprocessor has high and low power requirements corresponding to its two operating modes, and the deadman timer circuit also adjusts the output power level of an associated two-level power supply to ensure that sufficient power is available for the full operation of the microprocessor during reset. The deadman timer functions during both microprocessor modes and includes two level-sensitive input sections to ensure that the microprocessor is reset under an error condition.
摘要翻译：双重死机定时器电路用于在程序控制丢失的情况下复位双模微处理器。微处理器具有与其两种工作模式相对应的高功率和低功率要求，并且死机定时器电路还调整相关两级电源的输出功率电平，以确保在复位期间足够的功率可用于微处理器的全面操作。两个微处理器模式下的死机定时器功能包括两个电平敏感的输入部分，以确保微处理器在错误状态下复位。

3. 发明授权

US5764934A Processor subsystem for use with a universal computer architecture 失效
标题翻译：处理器子系统，用于通用计算机体系结构
公开(公告)号：US5764934A
公开(公告)日：1998-06-09
申请号：US675854
申请日：1996-07-03
申请人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
发明人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
IPC分类号： G06F13/36 , G06F13/38 , G06F13/40 , G06F13/42 , G06F15/76
CPC分类号： G06F13/4027
摘要： A processor subsystem includes a processor and a bus bridge conversion device for insertion into a slot of a host computer system. The processor operates according to a signaling protocol which is different than the signaling protocol of the computer system bus. The bus conversion device converts the signaling protocol of the system bus to the signaling protocol of the processor, and vice-versa. The bus conversion device includes logic for bus arbitration conversion, bus lock conversion, and cache coherency control. Logic is also included that converts incoming and outgoing requests so that the card may properly transact with other agents coupled to the bus.
摘要翻译：处理器子系统包括用于插入到主计算机系统的时隙中的处理器和总线桥转换装置。处理器根据与计算机系统总线的信令协议不同的信令协议进行操作。总线转换装置将系统总线的信令协议转换为处理器的信令协议，反之亦然。总线转换装置包括用于总线仲裁转换，总线锁转换和高速缓存一致性控制的逻辑。还包括逻辑，可转换传入和传出的请求，以便卡可以与耦合到总线的其他代理进行正确的交互。

4. 发明授权

US4355277A Dual mode DC/DC converter 失效
标题翻译：双模DC / DC转换器
公开(公告)号：US4355277A
公开(公告)日：1982-10-19
申请号：US192778
申请日：1980-10-01
申请人： Walter L. Davis , James E. Jacobson, Jr.
发明人： Walter L. Davis , James E. Jacobson, Jr.
IPC分类号： G05F1/56 , G05F3/20 , H02M3/155 , H02M3/156 , H02M3/335
CPC分类号： H02M3/156 , H02M2001/0032 , Y02B70/16
摘要： A DC/DC converter operates at peak efficiency in either of two output current level states in response to the power demands of an associated electronic device, thereby reducing wasted current to a minimum. The converter is designed to operate from a one-cell battery, and is particularly suited to an integrated circuit implementation.
摘要翻译：响应于相关联的电子设备的功率需求，DC / DC转换器以两个输出电流状态中的任一个工作在峰值效率，从而将浪费的电流减少到最小。该转换器设计为从单节电池工作，特别适用于集成电路实现。

5. 发明授权

US5845107A Signaling protocol conversion between a processor and a high-performance system bus 失效
标题翻译：处理器与高性能系统总线之间的信号协议转换
公开(公告)号：US5845107A
公开(公告)日：1998-12-01
申请号：US675679
申请日：1996-07-03
申请人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
发明人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
IPC分类号： G06F13/36 , G06F12/08 , G06F13/364 , G06F15/76
CPC分类号： G06F13/364
摘要： A method of operation in a computer system having a host processor, a pipelined system bus, and at least one agent, all of which operate in accordance with a first signaling protocol, and a processor that is included in a subsystem that operates according to a second signaling protocol which is incompatible with the first signaling protocol. The method comprises the steps of converting arbiter signals generated by the subsystem processor from the second signaling protocol to the first signaling protocol of the pipelined bus to obtain ownership of the pipelined bus. Next, an outgoing request encoding of the processor is translated from the second signaling protocol to the first signaling protocol. Finally, generating a bus cycle on the pipelined bus from the translated outgoing request encoding in accordance with the first signaling protocol of the pipelined bus.
摘要翻译：一种具有主处理器，流水线系统总线和至少一个代理的计算机系统中的操作方法，所有这些代理都按照第一信令协议进行操作，并且处理器包括在根据第二信令协议与第一信令协议不兼容。该方法包括以下步骤：将由子系统处理器产生的仲裁信号从第二信令协议转换为流水线总线的第一信令协议以获得流水线总线的所有权。接下来，将处理器的输出请求编码从第二信令协议转换为第一信令协议。最后，根据流水线总线的第一信令协议从流水线总线生成总线循环，根据翻译的输出请求编码。

6. 发明授权

US06424660B1 Addressable distributed wireless remote control system 失效
公开(公告)号：US06424660B1
公开(公告)日：2002-07-23
申请号：US08947738
申请日：1997-10-10
申请人： James E. Jacobson, Jr.
发明人： James E. Jacobson, Jr.
IPC分类号： H04Q706
摘要： An apparatus for use in an addressable distributed wireless remote control system includes a receiver operative to receive a request from an unidentified remote control device via a wireless communication medium. The apparatus also includes a storage device to store an identifier which identifies the receiver in the system, and transmit logic, coupled to the receiver and the storage medium, operative to transmit both the request and the identifier to a system controller.

7. 发明授权

US6079033A Self-monitoring distributed hardware systems 失效
标题翻译：自我监控分布式硬件系统
公开(公告)号：US6079033A
公开(公告)日：2000-06-20
申请号：US988771
申请日：1997-12-11
申请人： James E. Jacobson, Jr. , Robert P. Colwell
发明人： James E. Jacobson, Jr. , Robert P. Colwell
IPC分类号： G06F11/30 , G06F13/00
CPC分类号： G06F11/3055 , G06F11/0709 , G06F11/0757 , G06F11/0763 , G06F11/0793 , G06F11/3006
摘要： Each member system of a distributed collection of self-monitoring hardware systems includes receiving logic operative to receive a wellness token from a first other hardware system of the distributed collection of hardware systems. Each member system also includes modification logic, communicatively coupled to the receiving logic, operative to modify the wellness token to create a modified wellness token in a manner that reflects the wellness of the member hardware system, and transmitting logic, communicatively coupled to the modification logic, operative to transmit the modified wellness token to a second other hardware system of the distributed collection of hardware systems.
摘要翻译：分布式集合的自监控硬件系统的每个成员系统包括操作以从硬件系统的分布式集合的第一其他硬件系统接收健康令牌的接收逻辑。每个成员系统还包括通信地耦合到接收逻辑的修改逻辑，可操作以修改健康令牌以以反映成员硬件系统的健康的方式创建修改的健康令牌，以及通信地耦合到修改逻辑的发送逻辑操作以将修改的健康令牌传送到分布式硬件系统集合的另一个其他硬件系统。

8. 发明授权

US5896513A Computer system providing a universal architecture adaptive to a variety of processor types and bus protocols 失效
标题翻译：计算机系统提供了适用于各种处理器类型和总线协议的通用架构
公开(公告)号：US5896513A
公开(公告)日：1999-04-20
申请号：US675723
申请日：1996-07-03
申请人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
发明人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
IPC分类号： G06F13/16 , G06F13/18 , G06F13/36 , G06F13/40 , G06F13/14
CPC分类号： G06F13/4027 , G06F13/4063
摘要： A computer system providing a universal architecture includes a processor card connected to a system bus of a host computer system. The processor card is adapted for insertion into a slot of the computer system and houses a processor and a bus bridge conversion device. The processor operates according to a signaling protocol which is different than the signaling protocol of the computer system bus. The bus conversion device converts the signaling protocol of the system bus to the signaling protocol of the processor, and vice-versa. The bus conversion device includes logic for bus arbitration conversion, bus lock conversion, and cache coherency control. Logic is also included that converts incoming and outgoing requests so that the card may properly transact with other agents coupled to the bus.
摘要翻译：提供通用架构的计算机系统包括连接到主计算机系统的系统总线的处理器卡。处理器卡适于插入到计算机系统的插槽中并且容纳处理器和总线桥转换装置。处理器根据与计算机系统总线的信令协议不同的信令协议进行操作。总线转换装置将系统总线的信令协议转换为处理器的信令协议，反之亦然。总线转换装置包括用于总线仲裁转换，总线锁转换和高速缓存一致性控制的逻辑。还包括逻辑，可转换传入和传出的请求，以便卡可以与耦合到总线的其他代理进行正确的交互。

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