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1. 发明授权

US09601203B2 Floating gate non-volatile memory bit cell 有权
公开(公告)号：US09601203B2
公开(公告)日：2017-03-21
申请号：US13492811
申请日：2012-06-09
申请人： Mads Hommelgaard , Andrew Horch , Martin Niset
发明人： Mads Hommelgaard , Andrew Horch , Martin Niset
IPC分类号： H01L27/115 , G11C16/04 , H01L29/788 , H01L29/08
CPC分类号： H01L29/0847 , G11C16/0441 , H01L27/11524 , H01L27/1156 , H01L29/7881
摘要： A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes fabricating solid state device including NVM bit cell which provides multiple storage and includes an FET on substrate. The method also includes fabricating floating gate of the FET including thick gate oxide layer, and fabricating drain and source of FET within the substrate, drain and source coupled to the floating gate and channel region with native doping. Further, the method includes fabricating halo region within the substrate at the drain.

2. 发明申请

US20130328117A1 FLOATING GATE NON-VOLATILE MEMORY BIT CELL 有权
标题翻译：浮动门非易失性存储位单元
公开(公告)号：US20130328117A1
公开(公告)日：2013-12-12
申请号：US13492811
申请日：2012-06-09
申请人： Mads HOMMELGAARD , Andrew HORCH , Martin NISET
发明人： Mads HOMMELGAARD , Andrew HORCH , Martin NISET
IPC分类号： H01L27/105 , H01L21/8239
CPC分类号： H01L29/0847 , G11C16/0441 , H01L27/11524 , H01L27/1156 , H01L29/7881
摘要： A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes fabricating solid state device including NVM bit cell which provides multiple storage and includes an FET on substrate. The method also includes fabricating floating gate of the FET including thick gate oxide layer, and fabricating drain and source of FET within the substrate, drain and source coupled to the floating gate and channel region with native doping. Further, the method includes fabricating halo region within the substrate at the drain.
摘要翻译：固态非易失性存储器（NVM）器件包括存储器位单元。存储位单元包括制造在衬底上并具有浮置栅极的场效应晶体管（FET）。浮栅包括厚的氧化物层。 FET包括漏极和源极，每个都在衬底内制造并耦合到浮置栅极和具有天然掺杂的沟道区域。漏极被制造成具有卤素区域。制造固态NVM器件的方法包括制造包括提供多个存储并且在衬底上的FET的NVM位单元的固态器件。该方法还包括制造包括厚栅极氧化物层的FET的浮置栅极，并且在衬底内制造FET的漏极和源极，漏极和源极与天然掺杂耦合到浮置栅极和沟道区域。此外，该方法包括在漏极处制造衬底内的卤素区域。

3. 发明申请

US20070223276A1 Non-volatile memory wih controlled program/erase 有权
标题翻译：非易失性存储器控制程序/擦除
公开(公告)号：US20070223276A1
公开(公告)日：2007-09-27
申请号：US11385108
申请日：2006-03-21
申请人： Martin Niset , Derek Beattie , Andrew Birnie , Alistair Gorman , Stephen McGinty
发明人： Martin Niset , Derek Beattie , Andrew Birnie , Alistair Gorman , Stephen McGinty
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/3436 , G11C16/349
摘要： A method for programming/erasing a non-volatile memory (NVM) includes performing a program/erase operation on a portion of the NVM using a first set of parameters. The method further includes determining whether each cell in the portion of the NVM passes a first margin level, if not determining which one of a set of lower margin levels than the first margin level each cell in the portion of the NVM passes. The method further includes modifying at least one of the set of parameters associated with a subsequent program/erase operation for the portion of the NVM based on the determined one of the set of lower margin levels.
摘要翻译：用于编程/擦除非易失性存储器（NVM）的方法包括使用第一组参数对NVM的一部分执行编程/擦除操作。该方法还包括确定NVM的该部分中的每个小区是否通过第一边缘级别，如果不确定NVM的该部分中的每个小区的每个小区中的第一边缘级别的下边缘级别的哪一组中的哪一个。所述方法还包括基于所确定的所述一组下限级别来修改与所述NVM的所述部分的后续编程/擦除操作相关联的所述一组参数中的至少一个。

4. 发明申请

US20070058434A1 Nonvolatile memory cell programming 有权
标题翻译：非易失性存储单元编程
公开(公告)号：US20070058434A1
公开(公告)日：2007-03-15
申请号：US11209294
申请日：2005-08-23
申请人： Craig Cavins , Martin Niset , Laureen Parker
发明人： Craig Cavins , Martin Niset , Laureen Parker
IPC分类号： G11C16/04
CPC分类号： G11C16/0425 , G11C16/12
摘要： A method for programming a non-volatile memory (NVM) cell includes applying an increasing voltage to the current electrode that is used as a source during a read. The initial programming source voltage results in a relatively small number of electrons being injected into the storage layer. Because of the relatively low initial voltage level, the vertical field across the gate dielectric is reduced. The subsequent elevation of the source voltage does not raise the vertical field significantly due to the electrons in the storage layer establishing a field that reduces the vertical field. With less damage to the gate dielectric during programming, the endurance of the NVM cell is improved.
摘要翻译：一种用于对非易失性存储器（NVM）单元进行编程的方法包括：在读取期间向用作源的当前电极施加增加的电压。初始编程源电压导致相对少量的电子被注入到存储层中。由于初始电压电平相对较低，栅电介质的垂直场减小。由于存储层中的电子建立了减小垂直场的场，源电压的随后升高不会显着提高垂直场。在编程期间对栅极电介质的损害较小，NVM单元的耐久性得到改善。

5. 发明申请

US20070053222A1 Method and apparatus for programming/erasing a non-volatile memory 有权
公开(公告)号：US20070053222A1
公开(公告)日：2007-03-08
申请号：US11220733
申请日：2005-09-07
申请人： Martin Niset , Andrew Hardell
发明人： Martin Niset , Andrew Hardell
IPC分类号： G11C16/04
CPC分类号： G11C16/3436
摘要： A non-volatile memory (NVM) that can be optimized for data retention or endurance is divided into portions that are optimized for one or the other or potentially some other storage characteristic. For the portion allotted for data retention, the memory cells are erased to a relatively greater extent. For the portion allotted for high endurance, the memory cells are erased to a relatively lesser extent. This is conveniently achieved by simply raising the level of the current reference that is used to determine if a cell has been sufficiently erased for the high data retention cells. The higher endurance cells thus will typically receive fewer erase pulses than the memory cells for high data retention. The reduced erasing requirement for the high endurance cells results in overall faster erasing and less stress on the high endurance cells as well as on the circuitry that generates the high erase voltages.

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