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1. 发明授权

US07351614B1 Deep trench isolation for thyristor-based semiconductor device 失效
标题翻译：用于晶闸管的半导体器件的深沟槽隔离
公开(公告)号：US07351614B1
公开(公告)日：2008-04-01
申请号：US11230897
申请日：2005-09-20
申请人： Andrew Horch
发明人： Andrew Horch
IPC分类号： H01L21/332
CPC分类号： H01L29/41716 , H01L27/0617 , H01L27/0817 , H01L29/742
摘要： A thyristor-based semiconductor device includes a filled trench separating and electrically insulating adjacent thyristor control ports. According to an example embodiment of the present invention, the filled trench is formed in a substrate adjacent to at least one thyristor body region. The filled trench includes a conductive filler material, an insulative material formed on the conductive filler material and at least two laterally-adjacent thyristor control ports separated from one another by the conductive filler material and the insulative material. One of the control ports is adapted for capacitively coupling to the thyristor body region for controlling current in the thyristor. With this approach, two or more control ports can be formed in a single filled trench and electrically isolated by the conductive filler material/insulative material combination. In addition, the single filled trench can further be used to electrically isolate other circuitry, such as conductive shunts to buried circuit nodes in the substrate. These approaches are particularly useful, for example, in high-density applications where insulative trenches having high aspect ratios are desired (e.g., where it is difficult to fill lower portions of the trench with insulative material), and for reducing manufacturing complexity.
摘要翻译：一种基于晶闸管的半导体器件包括在相邻晶闸管控制端口之间分离和电绝缘的填充沟槽。根据本发明的示例性实施例，填充的沟槽形成在与至少一个晶闸管本体区域相邻的衬底中。填充的沟槽包括导电填充材料，形成在导电填料材料上的绝缘材料和通过导电填料和绝缘材料彼此分离的至少两个横向相邻的晶闸管控制端口。其中一个控制端口适于电容耦合到晶闸管主体区域以控制晶闸管中的电流。利用这种方法，可以在单个填充沟槽中形成两个或更多个控制端口，并通过导电填充材料/绝缘材料组合电隔离。此外，单个填充沟槽还可用于将其它电路（例如导电分流器）电隔离到衬底中的埋入电路节点。这些方法例如在需要具有高纵横比的绝缘沟槽（例如，难以用绝缘材料填充沟槽的下部）的高密度应用中以及用于降低制造复杂性方面特别有用。

2. 发明申请

US20060206277A1 Wireless functional testing of RFID tag 有权
标题翻译： RFID标签的无线功能测试
公开(公告)号：US20060206277A1
公开(公告)日：2006-09-14
申请号：US11069515
申请日：2005-02-28
申请人： Andrew Horch
发明人： Andrew Horch
IPC分类号： G01N37/00 , G08B13/14 , B07C5/344 , G01R31/28 , G01R31/302
CPC分类号： B07C5/344 , G01R31/01 , G01R31/2822 , H01L2223/6677 , Y10T29/49004
摘要： Wirelessly testing an RFID tag before it is packaged or otherwise entered into a process reserved for “working” RFID tags is described. Various processes that employ such wireless testing as well as various “on-die” RFID tag antennae designs for facilitating the wireless testing are also described.
摘要翻译：在将RFID标签封装或以其他方式输入到为“工作”RFID标签保留的过程中进行无线测试时，将进行描述。还描述了采用这种无线测试的各种过程以及用于促进无线测试的各种“裸片”RFID标签天线设计。

3. 发明授权

US06998652B1 Trench isolation for thyristor-based device 失效
标题翻译：基于晶闸管的器件的沟槽隔离
公开(公告)号：US06998652B1
公开(公告)日：2006-02-14
申请号：US10262729
申请日：2002-10-01
申请人： Andrew Horch , Scott Robins
发明人： Andrew Horch , Scott Robins
IPC分类号： H01L29/74 , H01L29/87
CPC分类号： H01L27/0629 , H01L27/0817 , H01L29/74
摘要： A semiconductor device includes a thyristor body having at least one region in a substrate. According to an example embodiment of the present invention, a trench is in a substrate and adjacent to a thyristor body region in the substrate. The trench is lined with an insulative material and further includes conductive material that is insulated from the thyristor body region in the substrate by the liner material. A conductive thyristor control port is located in the trench and adapted for capacitively coupling to the thyristor body region in the substrate and to control current in the thyristor body by causing an outflow of minority carriers in the thyristor. With this approach, conductive material can be used to fill a portion of the trench while using the trench portion including the conductive material to electrically isolate a portion of the thyristor body in the substrate. This approach is particularly useful, for example, in high-density applications where insulative trenches having high aspect ratios are desired.
摘要翻译：半导体器件包括在衬底中具有至少一个区域的晶闸管本体。根据本发明的示例性实施例，沟槽在衬底中并且与衬底中的可控硅体区相邻。沟槽衬有绝缘材料，并且还包括通过衬垫材料与衬底中的可控硅体区域绝缘的导电材料。导电晶闸管控制端口位于沟槽中，适于电容耦合到衬底中的晶闸管本体区域，并通过引起晶闸管中少数载流子的流出来控制晶闸管主体中的电流。利用这种方法，可以使用导电材料来填充沟槽的一部分，同时使用包括导电材料的沟槽部分来电隔离衬底中的可控硅体的一部分。这种方法在例如需要具有高纵横比的绝缘沟槽的高密度应用中是特别有用的。

4. 发明授权

US06980457B1 Thyristor-based device having a reduced-resistance contact to a buried emitter region 失效
标题翻译：具有与埋地发射极区域的电阻降低的接触的基于晶闸管的器件
公开(公告)号：US06980457B1
公开(公告)日：2005-12-27
申请号：US10288927
申请日：2002-11-06
申请人： Andrew Horch , Scott Robins
发明人： Andrew Horch , Scott Robins
IPC分类号： G11C11/39 , G11C17/06 , H01L27/102 , H01L27/105 , H01L27/108
CPC分类号： H01L27/105 , G11C11/39 , H01L27/1023 , H01L27/1027 , H01L27/108
摘要： A thyristor-based semiconductor device is formed having a thyristor, a pass device and an emitter region buried in a substrate and below at least one other vertically-arranged contiguous region of the thyristor that is at least partially below an upper surface of the substrate. According to an example embodiment of the present invention, a conductor, such as a polysilicon pillar formed in a trench, extends through the substrate and to the buried emitter region of the thyristor. In one implementation, a portion of the conductor includes a reduced-resistance material, such as a salicide, that is adapted to reduce the resistance of an electrical connection made to the buried emitter region via the conductor. This is particularly useful, for example, in connecting the buried emitter region to a power supply at a reduced resistance (e.g., as compared to the resistance that would be exhibited, were the reduced-resistance material not present).
摘要翻译：形成了一种晶闸管型半导体器件，其具有埋置在衬底中的晶闸管，通过器件和发射极区域，并且至少部分地在衬底的上表面下方的晶闸管的至少一个垂直布置的连续区域的下方。根据本发明的示例性实施例，形成在沟槽中的诸如多晶硅柱的导体延伸穿过衬底和晶闸管的掩埋发射极区。在一个实施方案中，导体的一部分包括抗电阻材料，例如自对准硅化物，其适于降低通过导体对掩埋发射极区域形成的电连接的电阻。这特别有用，例如，以降低的电阻（例如，与所显示的电阻相比，不存在耐电阻材料）将掩埋的发射极区域连接到电源。

5. 发明授权

US06965129B1 Thyristor-based device having dual control ports 失效
标题翻译：具有双控制端口的基于晶闸管的装置
公开(公告)号：US06965129B1
公开(公告)日：2005-11-15
申请号：US10288953
申请日：2002-11-06
申请人： Andrew Horch , Scott Robins , Farid Nemati
发明人： Andrew Horch , Scott Robins , Farid Nemati
IPC分类号： G11C11/39 , H01L21/8239 , H01L27/08 , H01L27/102 , H01L27/105 , H01L27/108 , H01L29/74
CPC分类号： G11C11/39 , H01L27/1025 , H01L27/1027 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L29/7436
摘要： Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor having first and second base regions coupled between first and second emitter regions, respectively. A first control port capacitively couples a first signal to the first base region, and a second control port capacitively couples a second signal to the second base region. Each of the first and second signals have a charge that is opposite in polarity, and the opposite polarity signals effect the switching of the thyristor at a lower power, relative to the power that would be required to switch the thyristor having only one control port. In this manner, power consumption for a switching operation can be reduced, which is useful, for example, to correspond with reduced power supplied to other devices in a semiconductor device employing the thyristor.
摘要翻译：使用适于在阻塞状态和导通状态之间切换的基于晶闸管的半导体器件来增强诸如存储器件中使用的切换操作。根据本发明的示例性实施例，基于晶闸管的半导体器件包括分别具有耦合在第一和第二发射极区之间的第一和第二基极区域的晶闸管。第一控制端口将第一信号电容耦合到第一基区，并且第二控制端口将第二信号电容耦合到第二基区。第一和第二信号中的每一个具有极性相反的电荷，相反的极性信号相对于仅具有一个控制端口的晶闸管所需的功率，以较低的功率影响晶闸管的开关。以这种方式，可以减少用于开关操作的功耗，这对于例如提供给采用晶闸管的半导体器件中的其它器件的降低的功率是有用的。

6. 发明授权

US06901021B1 Reference cells for TCCT based memory cells 失效
标题翻译：用于基于TCCT的存储单元的参考单元
公开(公告)号：US06901021B1
公开(公告)日：2005-05-31
申请号：US10838595
申请日：2004-05-04
申请人： Andrew Horch , Tapan Samaddar , Scott Robins
发明人： Andrew Horch , Tapan Samaddar , Scott Robins
IPC分类号： G11C7/14 , G11C7/00
CPC分类号： G11C7/14
摘要： A reference cell produces a reference current that is about half of the current produced by a memory cell. The reference cell is essentially the same as the memory cell with an additional current reduction device that can be a transistor. Adjusting a reference voltage applied to the transistor allows the reference current to be varied. A control circuit to produce the reference voltage includes dedicated memory and reference cells and a feedback circuit that compares the two cell' currents. The feedback circuit applies the reference voltage to the reference cell of the control circuit and adjusts the reference voltage until the current from the reference cell is about half of th current from the memory cell. The reference voltage is then applied to other reference cells in a memory array.
摘要翻译：参考单元产生约为由存储单元产生的电流的一半的参考电流。参考单元基本上与具有可以是晶体管的附加电流减小器件的存储器单元相同。调整施加到晶体管的参考电压允许参考电流变化。用于产生参考电压的控制电路包括专用存储器和参考单元以及比较两个单元电流的反馈电路。反馈电路将参考电压施加到控制电路的参考单元，并调整参考电压，直到来自参考单元的电流约为来自存储单元的电流的大约一半。然后将参考电压施加到存储器阵列中的其它参考单元。

7. 发明授权

US06818482B1 Method for trench isolation for thyristor-based device 失效
标题翻译：基于晶闸管的器件的沟槽隔离方法
公开(公告)号：US06818482B1
公开(公告)日：2004-11-16
申请号：US10263370
申请日：2002-10-01
申请人： Andrew Horch , Scott Robins
发明人： Andrew Horch , Scott Robins
IPC分类号： H01L21332
CPC分类号： H01L29/66363 , H01L21/76224 , H01L21/763 , H01L27/0817 , H01L29/41716 , H01L29/749
摘要： A semiconductor device includes a thyristor body having at least one region in a substrate. According to an example embodiment of the present invention, a trench is in a substrate and adjacent to a thyristor body region in the substrate. The trench is lined with an insulative material and further includes conductive material that is insulated from the thyristor body region in the substrate by the liner material. A conductive thyristor control port is located in the trench and adapted for capacitively coupling to the thyristor body region in the substrate and to control current in the thyristor body by causing an outflow of minority carriers in the thyristor. With this approach, conductive material can be used to fill a portion of the trench while using the trench portion including the conductive material to electrically isolate a portion of the thyristor body in the substrate. This approach is particularly useful, for example, in high-density applications where insulative trenches having high aspect ratios are desired.
摘要翻译：半导体器件包括在衬底中具有至少一个区域的晶闸管本体。根据本发明的示例性实施例，沟槽在衬底中并且与衬底中的可控硅体区相邻。沟槽衬有绝缘材料，并且还包括通过衬垫材料与衬底中的可控硅体区域绝缘的导电材料。导电晶闸管控制端口位于沟槽中，适于电容耦合到衬底中的晶闸管本体区域，并通过引起晶闸管中少数载流子的流出来控制晶闸管主体中的电流。利用这种方法，可以使用导电材料来填充沟槽的一部分，同时使用包括导电材料的沟槽部分来电隔离衬底中的可控硅体的一部分。这种方法在例如需要具有高纵横比的绝缘沟槽的高密度应用中是特别有用的。

8. 发明授权

US06686612B1 Thyristor-based device adapted to inhibit parasitic current 失效
标题翻译：适用于抑制寄生电流的基于晶闸管的器件
公开(公告)号：US06686612B1
公开(公告)日：2004-02-03
申请号：US10263382
申请日：2002-10-01
申请人： Andrew Horch , Scott Robins
发明人： Andrew Horch , Scott Robins
IPC分类号： H01L29423
CPC分类号： H01L27/0817 , H01L27/0629 , H01L29/87
摘要： Parasitic current leakage from a thyristor-based semiconductor device is inhibited. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor body portion and a control port located in a substrate, the control port being adapted for capacitively coupling to the thyristor body portion for controlling current flow therein. The substrate further includes a doped circuit region separated by a channel region from another doped region of similar polarity in the substrate. The control port faces the channel region in the substrate, and the channel region is susceptible to current leakage in response to voltage pulses being applied to the control port for controlling current flow in the thyristor. The device is arranged such that such current leakage in the channel is inhibited while pulses are applied to the control port for controlling current flow in the thyristor; the parasitic current leakage between the doped circuit region and the doped region in the substrate is inhibited.
摘要翻译：抑制了基于晶闸管的半导体器件的寄生电流泄漏。根据本发明的一个示例性实施例，一种基于晶闸管的半导体器件包括晶闸管主体部分和位于衬底中的控制端口，该控制端口适于与晶闸管主体部分电容耦合以控制其中的电流流动。衬底还包括由衬底中具有相似极性的另一个掺杂区域的沟道区域分离的掺杂电路区域。控制端口面向衬底中的沟道区域，并且响应于施加到控制端口的电压脉冲来控制电流流过晶闸管，沟道区域容易受到电流泄漏。该装置被布置为使得在控制端口处施加脉冲以控制晶闸管中的电流流动时，通道中的这种电流泄漏被抑制; 抑制了衬底中的掺杂电路区域和掺杂区域之间的寄生电流泄漏。

9. 发明授权

US06636442B2 Non-volatile memory element having a cascoded transistor scheme to reduce oxide field stress 失效
标题翻译：具有级联晶体管方案以减少氧化物场应力的非易失性存储元件
公开(公告)号：US06636442B2
公开(公告)日：2003-10-21
申请号：US10059624
申请日：2002-01-29
申请人： Michael Rowlandson , Andrew Horch
发明人： Michael Rowlandson , Andrew Horch
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/0433 , G11C16/3418
摘要： A non-volatile memory cell (FIG. 3) is provided which includes three transistors, a floating gate non-volatile storage transistor (303) and two cascode connected select transistors (301-302). The two cascoded select transistors (301-302) act together to block the programming voltage when the memory cell is included in an array, and the memory cell is not selected for programming. A value of an unselect voltage applied to the gate of the first cascode connected transistor (301) is set to prevent breakdown of the oxide in the first cascode transistor (301) as well as the second cascode transistor (302). A value of an unselect voltage applied to the gate of the second cascode connected transistor (302) can be selected so that the voltage passed to the floating gate storage transistor (303) will not result in a program drain disturb, or source disturb condition.
摘要翻译：提供了一种非易失性存储单元（图3），其包括三个晶体管，一个浮动非易失性非易失性存储晶体管（303）和两个共源共栅连接的选择晶体管（301-302）。当存储器单元包括在阵列中时，两个级联选择晶体管（301-302）一起起作用以阻止编程电压，并且不选择存储单元进行编程。设置施加到第一共源共栅晶体管（301）的栅极的未选择电压的值，以防止第一共源共栅晶体管（301）中的氧化物以及第二共源共栅晶体管（302）的击穿。可以选择施加到第二共源共栅晶体管（302）的栅极的取消选择电压的值，使得传递到浮置栅极存储晶体管（303）的电压不会导致编程漏极干扰或源干扰条件。

10. 发明申请

US20060125507A1 Wafer level testing for RFID tags 有权
标题翻译： RFID标签的晶圆级测试
公开(公告)号：US20060125507A1
公开(公告)日：2006-06-15
申请号：US11014523
申请日：2004-12-15
申请人： John Hyde , Robert Glidden , Andrew Horch , Jay Kuhn , Ronald Oliver
发明人： John Hyde , Robert Glidden , Andrew Horch , Jay Kuhn , Ronald Oliver
IPC分类号： G01R31/26
CPC分类号： G01R31/2822 , G01R31/2884 , G01R31/3025 , G01R31/318511
摘要： Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.
摘要翻译：披露了适用于无处不在的计算时代的在晶片测试的技术。所公开的发明特征之一是：1）用于并行测试测序的晶圆测试探针着陆区域的聚类; 2）在沿着晶片划线区域延伸的晶圆测试布线上; 3）晶片测试布线，可以刻划，但阻止污染物扩散到产品模具中; 4）RFID标签设计，允许进行片上测试而不施加实质的半导体表面积损失; 5）RFID标签设计，包括用于RFID标签的非易失性存储器的内置自检（BIST）电路。

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