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1. 发明授权

US07268394B2 JFET structure for integrated circuit and fabrication method 有权
标题翻译：集成电路和制造方法的JFET结构
公开(公告)号：US07268394B2
公开(公告)日：2007-09-11
申请号：US11038562
申请日：2005-01-18
申请人： Pinghai Hao , Fan-Chi Hou , Imran Khan
发明人： Pinghai Hao , Fan-Chi Hou , Imran Khan
IPC分类号： H01L29/76
CPC分类号： H01L27/085 , G11C2211/4068 , H01L21/8232 , H01L29/0692 , H01L29/1066 , H01L29/66901 , H01L29/808
摘要： Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.
摘要翻译：结型场效应晶体管（JFET）可以用形成足够厚的沟道区的外延层来制造，以使得JFET可用于高电压应用（例如具有大于约20V的击穿电压）。另外或替代地，可以在栅极，源极和漏极区域中的一个或多个处引入阈值电压（VT）注入，以改善JFET的噪声性能。另外，这样的JFET的制造可以促进与CMOS制造工艺和/或BiCMOS制造工艺同时形成整个JFET结构。

2. 发明授权

US07018880B2 Method for manufacturing a MOS transistor having reduced 1/f noise 有权
标题翻译：制造具有降低的1 / f噪声的MOS晶体管的方法
公开(公告)号：US07018880B2
公开(公告)日：2006-03-28
申请号：US10744549
申请日：2003-12-22
申请人： Pinghai Hao , Larry B. Anderson , Fan Chi Hou , Xiaoju Wu , Yvonne Patton , Shanjen Pan , Zafar Imam
发明人： Pinghai Hao , Larry B. Anderson , Fan Chi Hou , Xiaoju Wu , Yvonne Patton , Shanjen Pan , Zafar Imam
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/28176 , H01L21/265 , H01L21/28035 , H01L21/28061 , H01L21/823857 , H01L29/7833
摘要： The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (100). The method comprises forming an oxide layer (110) on a silicon substrate (105) and depositing a polysilicon layer (115) on the oxide layer (110). The method further includes implanting a fluorine dopant (130) into the polysilicon layer (115) at an implant dose of at least about 4×1014 atoms/cm2. The polysilicon layer (115) is thermally annealed such that a portion of the fluorine dopant (130) is diffused into the oxide layer (110) to thereby reduce a 1/f noise of the MOS device (100). Other embodiments of the provide a MOS device (300) manufactured by the above-described method and a method of manufacturing an integrated circuit (500) that includes the above-described method.
摘要翻译：本发明在一个实施例中提供一种降低金属氧化物半导体（MOS）器件（100）中的1 / f噪声的方法。该方法包括在硅衬底（105）上形成氧化物层（110）并在氧化物层（110）上沉积多晶硅层（115）。该方法还包括以至少约4×10 14原子/ cm 2的注入剂量将氟掺杂剂（130）注入到多晶硅层（115）中。多晶硅层（115）被热退火，使得氟掺杂剂（130）的一部分扩散到氧化物层（110）中，从而降低MOS器件（100）的1 / f噪声。提供通过上述方法制造的MOS器件（300）和包括上述方法的集成电路（500）的制造方法的其它实施例。

3. 发明授权

US08436635B2 Semiconductor wafer having test modules including pin matrix selectable test devices 有权
标题翻译：具有测试模块的半导体晶片包括引脚矩阵可选择的测试设备
公开(公告)号：US08436635B2
公开(公告)日：2013-05-07
申请号：US12552215
申请日：2009-09-01
申请人： Martin B. Mollat , Doug Weiser , Fan-Chi Hou
发明人： Martin B. Mollat , Doug Weiser , Fan-Chi Hou
IPC分类号： G01R31/02
CPC分类号： G01R31/2884 , G01R31/2831
摘要： A semiconductor wafer includes a plurality of die areas including circuit elements, and at least one test module (TM) on the wafer outside the die areas. The TMs include a test circuit including plurality of test transistors arranged in a plurality of rows and columns. The plurality of test transistors include at least three terminals (G, S, D and B). The TMs each include a plurality of pads. The pads include a first plurality of locally shared first pads each coupled to respective ones of a first of the three terminals, a second plurality of locally shared second pads each coupled to respective ones of a second of the three terminals, and at least one of the plurality of pads coupled to a third of the three terminals. The TM provides at least 2 pin transistor selection for uniquely selecting from the plurality of test transistors for testing.
摘要翻译：半导体晶片包括包括电路元件的多个管芯区域，以及在管芯区域外的晶片上的至少一个测试模块（TM）。 TM包括测试电路，该测试电路包括以多行和多列排列的多个测试晶体管。多个测试晶体管包括至少三个端子（G，S，D和B）。 TM各自包括多个垫。焊盘包括第一多个局部共享的第一焊盘，每个第一焊盘耦合到三个端子中的第一个端子中的相应的第一焊盘，第二多个局部共享的第二焊盘，每个第二焊盘耦合到三个端子中的第二个的相应的一个，所述多个焊盘耦合到三个端子中的三分之一。 TM提供至少2针晶体管选择，用于从多个测试晶体管中唯一地选择用于测试。

4. 发明申请

US20070218663A1 Semiconductor device incorporating fluorine into gate dielectric 审中-公开
标题翻译：将氟掺入栅极电介质的半导体器件
公开(公告)号：US20070218663A1
公开(公告)日：2007-09-20
申请号：US11384724
申请日：2006-03-20
申请人： Pinghai Hao , Imran Khan , Fan-Chi Hou
发明人： Pinghai Hao , Imran Khan , Fan-Chi Hou
IPC分类号： H01L21/425
CPC分类号： H01L21/28176 , H01L21/823857 , H01L21/8249 , H01L29/51 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The invention provides, in one aspect, a method of fabricating a semiconductor device. This embodiment comprises depositing a gate layer over a gate dielectric layer located over a semiconductor substrate, and incorporating fluorine into the gate dielectric layer before doping the gate layer.
摘要翻译：本发明在一个方面提供一种制造半导体器件的方法。该实施例包括在位于半导体衬底之上的栅极电介质层上沉积栅极层，并且在掺杂栅极层之前将氟掺杂到栅极介电层中。

5. 发明申请

US20050151171A1 JFET structure for integrated circuit and fabrication method 有权
公开(公告)号：US20050151171A1
公开(公告)日：2005-07-14
申请号：US11038562
申请日：2005-01-18
申请人： Pinghai Hao , Fan-Chi Hou , Imran Khan
发明人： Pinghai Hao , Fan-Chi Hou , Imran Khan
IPC分类号： H01L21/337 , H01L29/06 , H01L29/10 , H01L29/76 , H01L29/80 , H01L29/808
CPC分类号： H01L27/085 , G11C2211/4068 , H01L21/8232 , H01L29/0692 , H01L29/1066 , H01L29/66901 , H01L29/808
摘要： Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.

6. 发明授权

US06861303B2 JFET structure for integrated circuit and fabrication method 有权
标题翻译：集成电路和制造方法的JFET结构
公开(公告)号：US06861303B2
公开(公告)日：2005-03-01
申请号：US10434642
申请日：2003-05-09
申请人： Pinghai Hao , Fan-Chi Hou , Imran Khan
发明人： Pinghai Hao , Fan-Chi Hou , Imran Khan
IPC分类号： H01L21/337 , H01L29/06 , H01L29/10 , H01L29/76 , H01L29/80 , H01L29/808
CPC分类号： H01L27/085 , G11C2211/4068 , H01L21/8232 , H01L29/0692 , H01L29/1066 , H01L29/66901 , H01L29/808
摘要： Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.
摘要翻译：结型场效应晶体管（JFET）可以用形成足够厚的沟道区的外延层来制造，以使得JFET可用于高电压应用（例如具有大于约20V的击穿电压）。另外或替代地，可以在栅极，源极和漏极区域中的一个或多个处引入阈值电压（VT）注入，以改善JFET的噪声性能。另外，这样的JFET的制造可以促进与CMOS制造工艺和/或BiCMOS制造工艺同时形成整个JFET结构。

7. 发明申请

US20050136579A1 Method for manufacturing a metal oxide transistor having reduced 1/f noise 有权
标题翻译：制造具有降低的1 / f噪声的金属氧化物晶体管的方法
公开(公告)号：US20050136579A1
公开(公告)日：2005-06-23
申请号：US10744549
申请日：2003-12-22
申请人： Pinghai Hao , Larry Anderson , Fan Chi Hou , Xiaoju Wu , Yvonne Patton , Shanjen Pan , Zafar Imam
发明人： Pinghai Hao , Larry Anderson , Fan Chi Hou , Xiaoju Wu , Yvonne Patton , Shanjen Pan , Zafar Imam
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/28176 , H01L21/265 , H01L21/28035 , H01L21/28061 , H01L21/823857 , H01L29/7833
摘要： The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (100). The method comprises forming an oxide layer (110) on a silicon substrate (105) and depositing a polysilicon layer (115) on the oxide layer (110). The method further includes implanting a fluorine dopant (130) into the polysilicon layer (115) at an implant dose of at least about 4×1014 atoms/cm2. The polysilicon layer (115) is thermally annealed such that a portion of the fluorine dopant (130) is diffused into the oxide layer (110) to thereby reduce a 1/f noise of the MOS device (100). Other embodiments of the provide a MOS device (300) manufactured by the above-described method and a method of manufacturing an integrated circuit (500) that includes the above-described method.
摘要翻译：本发明在一个实施例中提供一种降低金属氧化物半导体（MOS）器件（100）中的1 / f噪声的方法。该方法包括在硅衬底（105）上形成氧化物层（110）并在氧化物层（110）上沉积多晶硅层（115）。该方法还包括以至少约4×10 14原子/ cm 2的注入剂量将氟掺杂剂（130）注入到多晶硅层（115）中。多晶硅层（115）被热退火，使得氟掺杂剂（130）的一部分扩散到氧化物层（110）中，从而降低MOS器件（100）的1 / f噪声。提供通过上述方法制造的MOS器件（300）和包括上述方法的集成电路（500）的制造方法的其它实施例。

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