会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明申请
    • Floating-point multiply-add unit using cascade design
    • 使用级联设计的浮点乘法单元
    • US20140188966A1
    • 2014-07-03
    • US13556710
    • 2012-07-24
    • Sameh GalalMark Horowitz
    • Sameh GalalMark Horowitz
    • G06F7/487G06F7/485
    • G06F7/5443G06F7/483G06F7/49947
    • A floating-point fused multiply-add (FMA) unit embodied in an integrated circuit includes a multiplier circuit cascaded with an adder circuit to produce a result A*C+B. To decrease latency, the FMA includes accumulation bypass circuits forwarding an unrounded result of the adder to inputs of the close path and the far path circuits of the adder, and forwarding an exponent result in carry save format to an input of the exponent difference circuit. Also included in the FMA is a multiply-add bypass circuit forwarding the unrounded result to the inputs of the multiplier circuit. The adder circuit includes an exponent difference circuit implemented in parallel with the multiplier circuit; a close path circuit implemented after the exponent difference circuit; and a far path circuit implemented after the exponent difference circuit.
    • 在集成电路中实现的浮点融合乘法(FMA)单元包括与加法器电路级联的乘法器电路,以产生结果A * C + B。 为了减少等待时间,FMA包括累加旁路电路,将加法器的未包围结果转发到加法器的关闭路径和远程路径电路的输入,并将指令结果以进位保存格式转发到指数差分电路的输入。 还包括在FMA中的是将不包围的结果转发到乘法器电路的输入的多路旁路电路。 加法器电路包括与乘法器电路并联实现的指数差电路; 在指数差分电路之后实现的闭路电路; 以及在指数差分电路之后实现的远程电路。