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1. 发明申请

US20080197497A1 BARRIER FOR USE IN 3-D INTEGRATION OF CIRCUITS 审中-公开
标题翻译：用于三维集成电路的障碍
公开(公告)号：US20080197497A1
公开(公告)日：2008-08-21
申请号：US12110009
申请日：2008-04-25
申请人： SCOTT K. POZDER , LYNNE M. MICHAELSON , VARUGHESE MATHEW
发明人： SCOTT K. POZDER , LYNNE M. MICHAELSON , VARUGHESE MATHEW
IPC分类号： H01L23/522
CPC分类号： H01L21/76898 , H01L21/76805 , H01L23/481 , H01L24/92 , H01L24/94 , H01L25/50 , H01L27/0688 , H01L2224/83191 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/14 , H01L2924/00
摘要： A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.
摘要翻译：一种形成半导体器件的方法包括提供具有着陆焊盘的第一集成电路，并且使用至少一个接合层将第二集成电路附接到第一集成电路。第二集成电路具有电路间迹线，电路间迹线具有电路间迹线开口。该方法还包括形成通过第二集成电路的开口，该开口延伸穿过该电路间开口，在该开口中的该电路间的迹线的暴露部分上形成选择性屏障，该开口通过该至少一个接合层到着陆垫，并用导电填充材料填充开口。选择性阻挡层包括钴或镍中的至少一种，并且导电填充材料电连接电路间迹线和着陆焊盘。

2. 发明授权

US07378339B2 Barrier for use in 3-D integration of circuits 有权
标题翻译：用于电路三维集成的屏障
公开(公告)号：US07378339B2
公开(公告)日：2008-05-27
申请号：US11278042
申请日：2006-03-30
申请人： Scott K. Pozder , Lynne M. Michaelson , Varughese Mathew
发明人： Scott K. Pozder , Lynne M. Michaelson , Varughese Mathew
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76898 , H01L21/76805 , H01L23/481 , H01L24/92 , H01L24/94 , H01L25/50 , H01L27/0688 , H01L2224/83191 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/14 , H01L2924/00
摘要： A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.
摘要翻译：一种形成半导体器件的方法包括提供具有着陆焊盘的第一集成电路，并且使用至少一个接合层将第二集成电路附接到第一集成电路。第二集成电路具有电路间迹线，电路间迹线具有电路间迹线开口。该方法还包括形成通过第二集成电路的开口，该开口延伸穿过该电路间开口，在该开口中的该电路间的迹线的暴露部分上形成选择性屏障，该开口通过该至少一个接合层到着陆垫，并用导电填充材料填充开口。选择性阻挡层包括钴或镍中的至少一种，并且导电填充材料电连接电路间迹线和着陆焊盘。

3. 发明授权

US07422979B2 Method of forming a semiconductor device having a diffusion barrier stack and structure thereof 有权
标题翻译：形成具有扩散阻挡叠层的半导体器件及其结构的方法
公开(公告)号：US07422979B2
公开(公告)日：2008-09-09
申请号：US11078236
申请日：2005-03-11
申请人： Lynne M. Michaelson , Edward Acosta , Ritwik Chatterjee , Stanley M. Filipiak , Sam S. Garcia , Varughese Mathew
发明人： Lynne M. Michaelson , Edward Acosta , Ritwik Chatterjee , Stanley M. Filipiak , Sam S. Garcia , Varughese Mathew
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76849 , H01L21/76822 , H01L21/76834 , H01L21/76835 , H01L21/76856
摘要： A diffusion barrier stack is formed by forming a layer comprising a metal over a conductor that includes copper; and forming a first dielectric layer over the layer, wherein the dielectric layer is of a thickness that alone it can not serve as a diffusion barrier layer to the conductor and the first dielectric layer prevents oxidation of the layer. In one embodiment, the diffusion barrier stack includes two layers; the first layer is a conductive layer and the second layer is a dielectric layer. The diffusion barrier stack minimizes electromigration and copper diffusion from the conductor.
摘要翻译：通过在包括铜的导体上形成包括金属的层来形成扩散阻挡叠层; 以及在所述层上形成第一电介质层，其中所述电介质层的厚度单独地不能用作所述导体的扩散阻挡层，并且所述第一介电层防止所述层的氧化。在一个实施例中，扩散阻挡堆叠包括两层; 第一层是导电层，第二层是电介质层。扩散阻挡层将导电体的电迁移和铜扩散最小化。

4. 发明授权

US07030001B2 Method for forming a gate electrode having a metal 失效
标题翻译：用于形成具有金属的栅电极的方法
公开(公告)号：US07030001B2
公开(公告)日：2006-04-18
申请号：US10827202
申请日：2004-04-19
申请人： Olubunmi O. Adetutu , Lynne M. Michaelson , Kathleen C. Yu , Robert E. Jones, Jr.
发明人： Olubunmi O. Adetutu , Lynne M. Michaelson , Kathleen C. Yu , Robert E. Jones, Jr.
IPC分类号： H01L21/3205
CPC分类号： H01L21/823842 , B82Y10/00 , B82Y30/00 , C23C16/042 , H01L21/28079 , H01L29/495 , H01L29/4958 , H01L29/7833
摘要： One embodiment forms a gate dielectric layer over a substrate and then selectively deposits a first metal layer over portions of the gate dielectric layer in which a first device type will be formed. A second metal layer, different from the first metal layer, is formed over exposed portions of the gate dielectric layer in which a second device type will be formed. Each of the first and second device types will have different work functions because each will include a different metal in direct contact with the gate dielectric. In one embodiment, the selective deposition of the first metal layer is performed by ALD and with the use of an inhibitor layer which is selectively formed over the gate dielectric layer such that the first metal layer may be selectively deposited on only those portions of the gate dielectric layer which are not covered by the inhibitor layer.
摘要翻译：一个实施例在衬底上形成栅极电介质层，然后在其中将形成第一器件类型的栅极电介质层的部分上选择性地沉积第一金属层。不同于第一金属层的第二金属层形成在将形成第二器件类型的栅极电介质层的暴露部分上。第一和第二装置类型中的每一种将具有不同的功函数，因为每个将包括与栅极电介质直接接触的不同金属。在一个实施例中，第一金属层的选择性沉积由ALD执行，并且使用抑制层，其选择性地形成在栅极电介质层上，使得第一金属层可以仅选择性地沉积在栅极的那些部分未被抑制层覆盖的介电层。

5. 发明授权

US08263430B2 Capping layer formation onto a dual damescene interconnect 有权
标题翻译：封盖层形成到双金属互连上
公开(公告)号：US08263430B2
公开(公告)日：2012-09-11
申请号：US12065190
申请日：2005-09-01
申请人： Janos Farkas , Lynne M Michaelson , Srdjan Kordic
发明人： Janos Farkas , Lynne M Michaelson , Srdjan Kordic
IPC分类号： H01L51/56
CPC分类号： H01L21/02074 , H01L21/288 , H01L21/3105 , H01L21/76801 , H01L21/76826 , H01L21/76849
摘要： A process for the formation of a capping layer on a conducting interconnect for a semiconductor device is provided, the process comprising the steps of: (a) providing one or more conductors in a dielectric layer, and (b) depositing a capping layer on an upper surface of at least some of the one or more conductors, characterized in that the process further includes: (c) the step of, prior to depositing the capping layer, reacting the dielectric layer with an organic compound in a liquid phase, the said organic compound having the following general formula: (I) where X is a functional group, R is an organic group or a organosiloxane group, Y1 is either a functional group or an organic group or organosiloxane group, and Y2 is either a functional group or an organic group or organosiloxane group, and where the functional group(s) is/are independently selected from the following: NH2, a secondary amine, a tertiary amine, acetamide, trifluoroacetamide, imidazole, urea, OH, an alkyoxy, acryloxy, acetate, SH, an alkylthiol, sulfonate, methanosulfonate, and cyanide, and salts thereof.
摘要翻译：提供了一种用于在半导体器件的导电互连上形成覆盖层的工艺，该方法包括以下步骤：（a）在电介质层中提供一个或多个导体，以及（b）将覆盖层沉积在所述一个或多个导体中的至少一些的上表面，其特征在于，所述方法还包括：（c）在沉积覆盖层之前使介电层与液相中的有机化合物反应的步骤，所述具有以下通式的有机化合物：（I）其中X是官能团，R是有机基团或有机硅氧烷基团，Y1是官能团或有机基团或有机硅氧烷基团，Y2是官能团或有机基团或有机硅氧烷基团，并且其中官能团独立地选自以下：NH 2，仲胺，叔胺，乙酰胺，三氟乙酰胺，咪唑，脲，OH，烷氧基，丙烯酸 xy，乙酸酯，SH，烷基硫醇，磺酸酯，甲磺酸酯和氰化物，及其盐。

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