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1. 发明授权

US07422979B2 Method of forming a semiconductor device having a diffusion barrier stack and structure thereof 有权
标题翻译：形成具有扩散阻挡叠层的半导体器件及其结构的方法
公开(公告)号：US07422979B2
公开(公告)日：2008-09-09
申请号：US11078236
申请日：2005-03-11
申请人： Lynne M. Michaelson , Edward Acosta , Ritwik Chatterjee , Stanley M. Filipiak , Sam S. Garcia , Varughese Mathew
发明人： Lynne M. Michaelson , Edward Acosta , Ritwik Chatterjee , Stanley M. Filipiak , Sam S. Garcia , Varughese Mathew
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76849 , H01L21/76822 , H01L21/76834 , H01L21/76835 , H01L21/76856
摘要： A diffusion barrier stack is formed by forming a layer comprising a metal over a conductor that includes copper; and forming a first dielectric layer over the layer, wherein the dielectric layer is of a thickness that alone it can not serve as a diffusion barrier layer to the conductor and the first dielectric layer prevents oxidation of the layer. In one embodiment, the diffusion barrier stack includes two layers; the first layer is a conductive layer and the second layer is a dielectric layer. The diffusion barrier stack minimizes electromigration and copper diffusion from the conductor.
摘要翻译：通过在包括铜的导体上形成包括金属的层来形成扩散阻挡叠层; 以及在所述层上形成第一电介质层，其中所述电介质层的厚度单独地不能用作所述导体的扩散阻挡层，并且所述第一介电层防止所述层的氧化。在一个实施例中，扩散阻挡堆叠包括两层; 第一层是导电层，第二层是电介质层。扩散阻挡层将导电体的电迁移和铜扩散最小化。

2. 发明授权

US07807572B2 Micropad formation for a semiconductor 有权
标题翻译：半导体的微阵列形成
公开(公告)号：US07807572B2
公开(公告)日：2010-10-05
申请号：US11969368
申请日：2008-01-04
申请人： Varughese Mathew , Eddie Acosta , Ritwik Chatterjee , Sam S. Garcia
发明人： Varughese Mathew , Eddie Acosta , Ritwik Chatterjee , Sam S. Garcia
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L24/81 , H01L2224/05001 , H01L2224/05026 , H01L2224/05027 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05572 , H01L2224/05611 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2224/81208 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/00014
摘要： A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips.
摘要翻译：一种方法形成微型至第一半导体器件的外部接触。在外部触点上形成铜钉。螺柱在第一半导体器件的表面之上延伸。将铜柱浸入锡溶液中。锡替代至少95％的螺柱铜，优选超过99％。结果是具有小于5重量％铜的锡微粉末。由于微电极基本上是纯锡，所以在第一半导体器件的微型焊盘未被接合的时间内，金属间键不会形成。因为不形成金属间键，因此产生较小的微尺寸尺寸。当第一半导体器件结合到上覆的第二半导体器件时，焊接尺寸不会显着增加堆叠芯片的高度。

3. 发明申请

US20090176366A1 MICROPAD FORMATION FOR A SEMICONDUCTOR 有权
标题翻译： MICROPAD形成一个半导体
公开(公告)号：US20090176366A1
公开(公告)日：2009-07-09
申请号：US11969368
申请日：2008-01-04
申请人： Varughese Mathew , Eddie Acosta , Ritwik Chatterjee , Sam S. Garcia
发明人： Varughese Mathew , Eddie Acosta , Ritwik Chatterjee , Sam S. Garcia
IPC分类号： H01L21/288
CPC分类号： H01L24/11 , H01L24/81 , H01L2224/05001 , H01L2224/05026 , H01L2224/05027 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05572 , H01L2224/05611 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2224/81208 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/00014
摘要： A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips.
摘要翻译：一种方法形成微型至第一半导体器件的外部接触。在外部触点上形成铜钉。螺柱在第一半导体器件的表面之上延伸。将铜柱浸入锡溶液中。锡替代至少95％的螺柱铜，优选超过99％。结果是具有小于5重量％铜的锡微粉末。由于微电极基本上是纯锡，所以在第一半导体器件的微型焊盘未被接合的时间内，金属间键不会形成。因为不形成金属间键，因此产生较小的微尺寸尺寸。当第一半导体器件结合到上覆的第二半导体器件时，焊接尺寸不会显着增加堆叠芯片的高度。

4. 发明授权

US07932175B2 Method to form a via 有权
标题翻译：形成通孔的方法
公开(公告)号：US07932175B2
公开(公告)日：2011-04-26
申请号：US11807745
申请日：2007-05-29
申请人： Ritwik Chatterjee , Eddie Acosta , Sam S. Garcia , Varughese Mathew
发明人： Ritwik Chatterjee , Eddie Acosta , Sam S. Garcia , Varughese Mathew
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898
摘要： A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.
摘要翻译：一种用于形成通孔的方法，包括（a）提供包括设置在半导体衬底（203）上的掩模（210）的结构，其中所述结构具有限定在其中的开口（215），所述开口延伸穿过所述掩模并进入所述衬底，并且其中所述掩模包括第一导电层; （b）沉积第二导电层（219），使得所述第二导电层与所述第一导电层电接触，所述第二导电层具有在所述开口的表面上延伸的第一部分，所述第二部分延伸在面罩的与开口相邻的一部分上方; （c）去除第二导电层的第二部分; 和（d）在第二导电层的第一部分上沉积第一金属（221）。

5. 发明申请

US20080299762A1 Method for forming interconnects for 3-D applications 有权
标题翻译：用于形成3-D应用的互连的方法
公开(公告)号：US20080299762A1
公开(公告)日：2008-12-04
申请号：US11807777
申请日：2007-05-29
申请人： Varughese Mathew , Eddie Acosta , Ritwik Chatterjee , Sam S. Garcia
发明人： Varughese Mathew , Eddie Acosta , Ritwik Chatterjee , Sam S. Garcia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898
摘要： A method for forming an interconnect, comprising (a) providing a substrate (203) with a via (205) defined therein; (b) forming a seed layer (211) such that a first portion of the seed layer extends over a surface of the via, and a second portion of the seed layer extends over a portion of the substrate; (c) removing the second portion of the seed layer; and (d) depositing a metal (215) over the first portion of the seed layer by an electroless process.
摘要翻译：一种用于形成互连的方法，包括：（a）提供具有在其中限定的通孔（205）的衬底（203）; （b）形成晶种层（211），使种子层的第一部分在通孔的表面上延伸，种子层的第二部分延伸到衬底的一部分上; （c）去除种子层的第二部分; 和（d）通过无电解方法在种子层的第一部分上沉积金属（215）。

6. 发明授权

US07572723B2 Micropad for bonding and a method therefor 有权
标题翻译：用于粘合的Micropad及其方法
公开(公告)号：US07572723B2
公开(公告)日：2009-08-11
申请号：US11552821
申请日：2006-10-25
申请人： Varughese Mathew , Eddie Acosta , Ritwik Chatterjee , Sam S. Garcia
发明人： Varughese Mathew , Eddie Acosta , Ritwik Chatterjee , Sam S. Garcia
IPC分类号： H01L21/4763
CPC分类号： H01L24/11 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01024 , H01L2924/01025 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01327 , H01L2924/14
摘要： A semiconductor process is taught for performing electroless plating of copper overlying at least a portion of a layer comprising cobalt, nickel, or both cobalt and nickel. The cobalt and/or nickel comprising layer may be formed using electroless plating. For some embodiments, a tin layer is then formed overlying the copper. The tin layer may be formed using immersion plating or electroless plating. A micropad may comprise the cobalt and/or nickel comprising layer and the copper layer. In some embodiments, the micropad may also comprise the tin layer. In one embodiment, the micropad may be compressed at an elevated temperature to form a copper tin intermetallic compound which provides an interconnect between a plurality of semiconductor devices.
摘要翻译：教导了一种半导体工艺，用于执行铜覆盖至少部分钴，镍或钴和镍两者的层的化学镀。可以使用无电镀形成包含钴和/或镍的层。对于一些实施例，然后形成覆盖铜的锡层。锡层可以使用浸镀或无电镀形成。微孔可以包括包含钴和/或镍的层和铜层。在一些实施方案中，微团也可包含锡层。在一个实施例中，微塔可以在升高的温度下被压缩以形成提供多个半导体器件之间的互连的铜锡金属间化合物。

7. 发明授权

US08586474B2 Method to form a via 有权
标题翻译：形成通孔的方法
公开(公告)号：US08586474B2
公开(公告)日：2013-11-19
申请号：US13040797
申请日：2011-03-04
申请人： Ritwik Chatterjee , Eddie Acosta , Sam S. Garcia , Varughese Mathew
发明人： Ritwik Chatterjee , Eddie Acosta , Sam S. Garcia , Varughese Mathew
IPC分类号： H01L21/44
CPC分类号： H01L21/76898
摘要： A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.
摘要翻译：一种用于形成通孔的方法，包括（a）提供包括设置在半导体衬底（203）上的掩模（210）的结构，其中所述结构具有限定在其中的开口（215），所述开口延伸穿过所述掩模并进入所述衬底，并且其中所述掩模包括第一导电层; （b）沉积第二导电层（219），使得所述第二导电层与所述第一导电层电接触，所述第二导电层具有在所述开口的表面上延伸的第一部分，所述第二部分延伸在面罩的与开口相邻的一部分上方; （c）去除第二导电层的第二部分; 和（d）在第二导电层的第一部分上沉积第一金属（221）。

8. 发明申请

US20080299759A1 Method to form a via 有权
标题翻译：形成通孔的方法
公开(公告)号：US20080299759A1
公开(公告)日：2008-12-04
申请号：US11807745
申请日：2007-05-29
申请人： Ritwik Chatterjee , Eddie Acosta , Sam S. Garcia , Varughese Mathew
发明人： Ritwik Chatterjee , Eddie Acosta , Sam S. Garcia , Varughese Mathew
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898
摘要： A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.
摘要翻译：一种用于形成通孔的方法，包括（a）提供包括设置在半导体衬底（203）上的掩模（210）的结构，其中所述结构具有限定在其中的开口（215），所述开口延伸穿过所述掩模并进入所述衬底，并且其中所述掩模包括第一导电层; （b）沉积第二导电层（219），使得所述第二导电层与所述第一导电层电接触，所述第二导电层具有在所述开口的表面上延伸的第一部分，所述第二部分延伸在面罩的与开口相邻的一部分上方; （c）去除第二导电层的第二部分; 和（d）在第二导电层的第一部分上沉积第一金属（221）。

9. 发明申请

US20080099799A1 MICROPAD FOR BONDING AND A METHOD THEREFOR 有权
标题翻译：用于结合的微波炉及其方法
公开(公告)号：US20080099799A1
公开(公告)日：2008-05-01
申请号：US11552821
申请日：2006-10-25
申请人： Varughese Mathew , Eddie Acosta , Ritwik Chatterjee , Sam S. Garcia
发明人： Varughese Mathew , Eddie Acosta , Ritwik Chatterjee , Sam S. Garcia
IPC分类号： H01L29/80 , H01L31/112 , H01L21/331 , H01L21/8222
CPC分类号： H01L24/11 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01024 , H01L2924/01025 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01327 , H01L2924/14
摘要： A semiconductor process is taught for performing electroless plating of copper overlying at least a portion of a layer comprising cobalt, nickel, or both cobalt and nickel. The cobalt and/or nickel comprising layer may be formed using electroless plating. For some embodiments, a tin layer is then formed overlying the copper. The tin layer may be formed using immersion plating or electroless plating. A micropad may comprise the cobalt and/or nickel comprising layer and the copper layer. In some embodiments, the micropad may also comprise the tin layer. In one embodiment, the micropad may be compressed at an elevated temperature to form a copper tin intermetallic compound which provides an interconnect between a plurality of semiconductor devices.
摘要翻译：教导了一种半导体工艺，用于执行铜覆盖至少部分钴，镍或钴和镍两者的层的化学镀。可以使用无电镀形成包含钴和/或镍的层。对于一些实施例，然后形成覆盖铜的锡层。锡层可以使用浸镀或无电镀形成。微孔可以包括包含钴和/或镍的层和铜层。在一些实施方案中，微团也可包含锡层。在一个实施例中，微塔可以在升高的温度下被压缩以形成提供多个半导体器件之间的互连的铜锡金属间化合物。

10. 发明授权

US08003517B2 Method for forming interconnects for 3-D applications 有权
标题翻译：用于形成3-D应用的互连的方法
公开(公告)号：US08003517B2
公开(公告)日：2011-08-23
申请号：US11807777
申请日：2007-05-29
申请人： Varughese Mathew , Eddie Acosta , Ritwik Chatterjee , Sam S. Garcia
发明人： Varughese Mathew , Eddie Acosta , Ritwik Chatterjee , Sam S. Garcia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898
摘要： A method for forming an interconnect, comprising (a) providing a substrate (203) with a via (205) defined therein; (b) forming a seed layer (211) such that a first portion of the seed layer extends over a surface of the via, and a second portion of the seed layer extends over a portion of the substrate; (c) removing the second portion of the seed layer; and (d) depositing a metal (215) over the first portion of the seed layer by an electroless process.
摘要翻译：一种用于形成互连的方法，包括：（a）提供具有在其中限定的通孔（205）的衬底（203）; （b）形成晶种层（211），使种子层的第一部分在通孔的表面上延伸，种子层的第二部分延伸到衬底的一部分上; （c）去除种子层的第二部分; 和（d）通过无电解方法在种子层的第一部分上沉积金属（215）。

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