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1. 发明申请

US20060106991A1 Victim prefetching in a cache hierarchy 失效
标题翻译：受害者在缓存层次结构中预取
公开(公告)号：US20060106991A1
公开(公告)日：2006-05-18
申请号：US10989997
申请日：2004-11-16
申请人： Peter Franaszek , Steven Kunkel , Luis Lastras Montano , Aaron Sawdey
发明人： Peter Franaszek , Steven Kunkel , Luis Lastras Montano , Aaron Sawdey
IPC分类号： G06F12/00
CPC分类号： G06F12/122 , G06F12/0862 , G06F12/0897
摘要： We present a “directory extension” (hereinafter “DX”) to aid in prefetching between proximate levels in a cache hierarchy. The DX may maintain (1) a list of pages which contains recently ejected lines from a given level in the cache hierarchy, and (2) for each page in this list, the identity of a set of ejected lines, provided these lines are prefetchable from, for example, the next level of the cache hierarchy. Given a cache fault to a line within a page in this list, other lines from this page may then be prefetched without the substantial overhead to directory lookup which would otherwise be required.
摘要翻译：我们提出一个“目录扩展名”（以下简称“DX”）来辅助缓存层级中的邻近级别之间的预取。 DX可以维护（1）包含最近从缓存层级中的给定级别排出的行的页面列表，以及（2）对于该列表中的每个页面，提供这些行是可预取的集合的标识从例如缓存层次结构的下一级。给定列表中页面内的行的高速缓存错误，然后可以预取此页面中的其他行，而不需要大量开销，否则将需要目录查找。

2. 发明申请

US20050235115A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR MEMORY MANAGEMENT 失效
标题翻译：用于内存管理的系统，方法和存储介质
公开(公告)号：US20050235115A1
公开(公告)日：2005-10-20
申请号：US10709128
申请日：2004-04-15
申请人： Peter Franaszek , Luis Lastras
发明人： Peter Franaszek , Luis Lastras
IPC分类号： G06F12/08 , G06F12/00 , G06F12/12
CPC分类号： G06F12/0862 , G06F12/0895 , G06F2212/1024 , G06F2212/502 , G06F2212/6022 , G06F2212/6024
摘要： A system for memory management including a tag controlled buffer in communication with a memory device. The memory device includes a plurality of pages divided into a plurality of individually addressable lines. The tag controlled buffer includes a prefetch buffer including at least one of the individually addressable lines from the memory device. The tag controlled buffer also includes a tag cache in communication with the prefetch buffer. The tag cache includes a plurality of tags, where each tag is associated with one of the pages in the memory device and each tag includes a pointer to at least one of the lines in the prefetch buffer. Access to the lines in the prefetch buffer is controlled by the tag cache.
摘要翻译：一种用于存储器管理的系统，包括与存储器件通信的标签控制缓冲器。存储装置包括被分成多个可单独寻址的行的多个页面。标签控制缓冲器包括预取缓冲器，其包括来自存储器装置的至少一个可单独寻址的线路。标签控制缓冲器还包括与预取缓冲器通信的标签缓存。标签缓存包括多个标签，其中每个标签与存储器设备中的一个页面相关联，并且每个标签包括指向预取缓冲器中的至少一行的指针。访问预取缓冲区中的行由标记缓存控制。

3. 发明授权

US08640065B2 Circuit verification using computational algebraic geometry 有权
标题翻译：使用计算代数几何的电路验证
公开(公告)号：US08640065B2
公开(公告)日：2014-01-28
申请号：US13360083
申请日：2012-01-27
申请人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
发明人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504
摘要： In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：接收对要对其进行验证的多个输入的操作的电路的第一描述; 接收对所述电路的预期行为的第二描述，其中所述第二描述中的预期行为被表示为在至少一个伽罗瓦域上的多变量多项式的代数系统集合; 将至少一个计算代数几何技术应用于第一描述和第二描述的组合以确定电路是否被验证，其中电路的验证确认基于第一描述获得的至少一个输出对应于至少一个预期的基于在第二描述中表达的预期行为的价值; 并且输出关于电路是否被验证的指示。

4. 发明申请

US20080059714A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR PREFETCHING VIA MEMORY BLOCK TAGS 有权
标题翻译：用于通过存储块标签进行预制的系统，方法和存储介质
公开(公告)号：US20080059714A1
公开(公告)日：2008-03-06
申请号：US11936414
申请日：2007-11-07
申请人： Peter Franaszek , Luis Lastras
发明人： Peter Franaszek , Luis Lastras
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0862
摘要： A system for memory management including a tag cache in communication with one or more cache devices in a storage hierarchy is provided. The tag cache includes tags of recently accessed memory blocks, each tag corresponding to one of the memory blocks and each tag including tag contents. The tag contents include a memory block real address and one bit for every memory line in the memory block. The bits are referred to as prefetch bits. Each of the prefetch bits is reset to a non-prefetch status with a selected probability of between zero and one. The tag contents control which memory lines of the corresponding memory block are prefetched into at least one of the cache devices. The tag contents are updated using a selected subset of processor references. The subset is referred to as filtered references. The tag contents are modified probabilistically at selected times or events.
摘要翻译：提供了一种用于存储器管理的系统，其包括与存储层级中的一个或多个高速缓存设备通信的标签高速缓存。标签缓存包括最近访问的存储块的标签，每个标签对应于一个存储器块，每个标签包括标签内容。标签内容包括存储器块实际地址和存储器块中每个存储器线的一位。这些位被称为预取位。每个预取位被复位到具有0和1之间的所选概率的非预取状态。标签内容控制对应的存储器块的哪些存储器行被预取到至少一个高速缓存器件中。使用选定的处理器引用子集来更新标签内容。该子集称为过滤引用。标签内容在选定的时间或事件中被概率地修改。

5. 发明申请

US20130198705A1 CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY 有权
标题翻译：使用计算代数几何的电路验证
公开(公告)号：US20130198705A1
公开(公告)日：2013-08-01
申请号：US13360083
申请日：2012-01-27
申请人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
发明人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：接收对要对其进行验证的多个输入的操作的电路的第一描述; 接收对所述电路的预期行为的第二描述，其中所述第二描述中的预期行为被表示为在至少一个伽罗瓦域上的多变量多项式的代数系统集合; 将至少一个计算代数几何技术应用于第一描述和第二描述的组合以确定电路是否被验证，其中电路的验证确认基于第一描述获得的至少一个输出对应于至少一个预期的基于在第二描述中表达的预期行为的价值; 并且输出关于电路是否被验证的指示。

6. 发明申请

US20070204109A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR PREFETCHING VIA MEMORY BLOCK TAGS 有权
标题翻译：用于通过存储块标签进行预制的系统，方法和存储介质
公开(公告)号：US20070204109A1
公开(公告)日：2007-08-30
申请号：US11743697
申请日：2007-05-03
申请人： Peter Franaszek , Luis Lastras
发明人： Peter Franaszek , Luis Lastras
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： A method and system for memory management are provided. The system includes a tag cache in communication with one or more cache devices in a storage hierarchy. The tag cache includes tags of recently accessed memory blocks, each tag corresponding to one of the memory blocks and including tag contents. The tag contents control which memory lines of the corresponding memory block are prefetched into at least one of the cache devices. The tag contents further include a bit to control prefetching of memory lines from a next virtual memory block, the bit referred to as a next virtual memory block bit. The next virtual memory block bit in a preceding memory block in a virtual address space is set to a prefetch status when the preceding memory block tag is in the tag cache.
摘要翻译：提供了一种用于存储器管理的方法和系统。该系统包括与存储层级中的一个或多个缓存设备通信的标签缓存。标签缓存包括最近访问的存储器块的标签，每个标签对应于一个存储器块并且包括标签内容。标签内容控制对应的存储器块的哪些存储器行被预取到至少一个高速缓存器件中。标签内容还包括用于控制来自下一个虚拟存储器块的存储器行预取的位，该位被称为下一个虚拟存储器块位。虚拟地址空间中前一个存储块中的下一个虚拟内存块位被设置为当前一个存储块标记位于标记高速缓存中时的预取状态。

7. 发明申请

US20050050404A1 Apparatus and method for detecting and forecasting resource bottlenecks 有权
标题翻译：检测和预测资源瓶颈的装置和方法
公开(公告)号：US20050050404A1
公开(公告)日：2005-03-03
申请号：US10647800
申请日：2003-08-25
申请人： Vittorio Castelli , Peter Franaszek , Luis Lastras
发明人： Vittorio Castelli , Peter Franaszek , Luis Lastras
IPC分类号： G06F11/00 , G06F11/34
CPC分类号： G06F11/3409 , G06F11/3452 , G06F2201/81
摘要： A system and method of detecting and forecasting resource bottlenecks of a computer system. In one aspect, a method comprises the steps of: monitoring with successive measurements a utilization parameter of a system resource; computing a change parameter by comparing the differences between successive measurements of the utilization parameter; comparing the change parameter to a threshold change parameter; and reporting a resource bottleneck if the change parameter exceeds the threshold change parameter.
摘要翻译：一种检测和预测计算机系统资源瓶颈的系统和方法。一方面，一种方法包括以下步骤：通过连续测量监视系统资源的利用参数; 通过比较使用参数的连续测量之间的差异来计算变化参数; 将变化参数与阈值变化参数进行比较; 并且如果改变参数超过阈值变化参数则报告资源瓶颈。

8. 发明申请

US20070230353A1 METHOD AND APPARATUS FOR COST-EFFECTIVE DESIGN OF LARGE-SCALE SENSOR NETWORKS 有权
标题翻译：大规模传感器网络成本有效设计的方法与装置
公开(公告)号：US20070230353A1
公开(公告)日：2007-10-04
申请号：US11692874
申请日：2007-03-28
申请人： Akshay Kashyap , Luis Lastras-Montano , Zhen Liu , Honghui Xia
发明人： Akshay Kashyap , Luis Lastras-Montano , Zhen Liu , Honghui Xia
IPC分类号： H04J3/14 , H04J1/16
CPC分类号： H04L67/12
摘要： Arrangements and methods for developing a software toolkit that can be used to design or obtain parameters for a sensor network. High-level guidelines on the basic relations between sensor network parameters like number of sensors, degree of quantization at each sensor, and the distortion requirements, based on a deep analysis on two basic coding possibilities (multiplexed point-to-point, distributed) are contemplated. By evaluating tradeoffs among the various parameters, an optimization framework to obtain the most cost-effective design with required quantization capabilities pertaining to given distortion criterion is provided.
摘要翻译：用于开发可用于设计或获取传感器网络参数的软件工具包的安排和方法。基于对两种基本编码可能性（多点对点，分布式）的深入分析，关于传感器网络参数（如传感器数量，每个传感器的量化度和失真要求）之间的基本关系的高级指南是预期。通过评估各种参数之间的折衷，提供了一种优化框架，以获得具有与给定失真标准相关的所需量化能力的最具成本效益的设计。

9. 发明申请

US20050235116A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR PREFETCHING VIA MEMORY BLOCK TAGS 有权
标题翻译：用于通过存储块标签进行预制的系统，方法和存储介质
公开(公告)号：US20050235116A1
公开(公告)日：2005-10-20
申请号：US10709127
申请日：2004-04-15
申请人： Peter Franaszek , Luis Lastras
发明人： Peter Franaszek , Luis Lastras
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862
摘要： A system for memory management including a tag cache in communication with one or more cache devices in a storage hierarchy. The tag cache includes tags of recently accessed memory blocks where each tag corresponds to one of the pages and each tag includes tag contents. The tag contents control which memory lines of the corresponding memory block are prefetched into at least one of the cache devices. The tag contents are updated using a selected subset of processor references. The subset is referred to as filtered references. The tag contents are modified probabilistically at selected time or events.
摘要翻译：一种用于存储器管理的系统，包括与存储层级中的一个或多个高速缓存设备通信的标签缓存。标签缓存包括最近访问的存储器块的标签，其中每个标签对应于其中一个页面，并且每个标签包括标签内容。标签内容控制对应的存储器块的哪些存储器行被预取到至少一个高速缓存器件中。使用选定的处理器引用子集来更新标签内容。该子集称为过滤引用。标签内容在选定的时间或事件中被概率地修改。

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