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    • 9. 发明授权
    • Vertical PNP transistor in merged bipolar/CMOS technology
    • 并联双极/ CMOS技术中的垂直PNP晶体管
    • US5455447A
    • 1995-10-03
    • US954605
    • 1992-09-30
    • Louis N. HutterJoe R. Trogolo
    • Louis N. HutterJoe R. Trogolo
    • H01L27/06H01L29/732H01L29/72H01L27/10H01L27/15
    • H01L29/7322H01L27/0623
    • A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried layer (82) and upwards into a P- epitaxy layer (52d) and into a base region (54c). The base region (54c) is formed in the same processing step as the N well region (54b) of the PMOS transistor (42) and the collection region (54a) of the NPN transistor (40). By diffusing into the base region (54c), the width between the collector (84) and emitter (64e) is reduced. The emitter (64e) can be formed in conjunction with the source and drain regions of the PMOS transistor (42). The vertical PNP transistor (46) is laterally isolated from the other transistor devices by an annular ring formed from an N+ region (50c) formed in conjunction with an N+ DUF region (50a) used in the NPN transistor (40), and a N+ region (56b) formed in conjunction with an N+ collector region (56a) of the NPN transistor (40). An N+ DUF region (50b) may also be used in connection with the PMOS transistor (42).
    • 用于合并双极/ CMOS技术的垂直PNP结构具有作为集电极区的P +掩埋层(84),其通过N-掩埋层(82)与P衬底(48)隔离。 P +掩埋层(84)向下扩散到N埋层(82)中并向上扩散到P-外延层(52d)中并进入基极区(54c)。 基极区域(54c)以与PMOS晶体管(42)的N阱区域(54b)和NPN晶体管(40)的收集区域(54a)相同的处理步骤形成。 通过扩散到基极区域(54c)中,收集器(84)和发射极(64e)之间的宽度减小。 发射极(64e)可以与PMOS晶体管(42)的源极和漏极区域结合形成。 垂直PNP晶体管(46)通过由与NPN晶体管(40)中使用的N + DUF区域(50a)形成的N +区域(50c)形成的环形环与其它晶体管器件横向隔离,并且N + 区域(56b)与NPN晶体管(40)的N +集电极区(56a)结合形成。 N + DUF区(50b)也可以与PMOS晶体管(42)结合使用。