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1. 发明授权

US07562315B2 Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout 有权
标题翻译：基于边缘识别的高电压伪层验证方法，用于混合信号设计布局
公开(公告)号：US07562315B2
公开(公告)日：2009-07-14
申请号：US11199337
申请日：2005-08-08
申请人： Lily X. Springer , Haim Horovitz , Robert Graham Shaw, Jr. , Sameer Pendharkar , Wen-Hwa M. Chu , Paul C. Mannas
发明人： Lily X. Springer , Haim Horovitz , Robert Graham Shaw, Jr. , Sameer Pendharkar , Wen-Hwa M. Chu , Paul C. Mannas
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage dependent design rule is applied to an edge of an area of the layout if the edge is not covered by a pseudo layer. A second voltage dependent design rule is, on the other hand, applied to the edge of the area if the edge is covered by the pseudo layer.
摘要翻译：公开了所提出的半导体设计布局中的至少一些的验证。根据本发明的一个或多个方面，如果边缘未被伪层覆盖，则将第一电压依赖设计规则应用于布局区域的边缘。另一方面，如果边缘被伪层覆盖，则第二电压依赖设计规则被应用于该区域的边缘。

2. 发明授权

US07398493B2 Isolated pwell tank verification using node breakers 有权
标题翻译：使用节点断路器进行隔离池验证
公开(公告)号：US07398493B2
公开(公告)日：2008-07-08
申请号：US11374259
申请日：2006-03-13
申请人： Haim Horovitz , Mark Allenspach , Peter Fleischmann
发明人： Haim Horovitz , Mark Allenspach , Peter Fleischmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A technique for checking a layout design of an integrated circuit is disclosed. The technique has application to converting the design of a circuit from schematic to layout form. Instances where multiple pwell isolation tanks are coupled to the same node and where one or more pwell isolation tanks are shorted to a substrate are detected. Node breakers are inserted in the layout between pwell isolation tanks coupled to the same node and between the substrate and isolated pwell tanks coupled to the substrate. The node breakers are inserted in the circuit schematic as well to satisfy a layout versus schematic comparison. Inserting the node breakers highlights circuit component groupings as well as which tanks contain certain elements, if any. This allows designers to make a conscious decision as to the location and groupings of elements in a layout design.
摘要翻译：公开了一种用于检查集成电路的布局设计的技术。该技术具有将电路设计从原理图转换为布局形式的应用。检测到多个孔隔离槽耦合到同一节点并且其中一个或多个孔隔离槽与基板短接的实例。节点断路器插入在连接到同一节点的隔离隔离槽之间以及耦合到基板的基板和隔离的储池之间的布局中。节点断路器也插入到电路原理图中，以满足布局与原理图比较。插入节点断路器突出显示电路组件分组，以及哪些坦克包含某些元素（如果有）。这使得设计者能够对布局设计中元素的位置和分组做出有意识的决定。

3. 发明申请

US20070033556A1 Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout 有权
标题翻译：基于边缘识别的高电压伪层验证方法，用于混合信号设计布局
公开(公告)号：US20070033556A1
公开(公告)日：2007-02-08
申请号：US11199337
申请日：2005-08-08
申请人： Lily Springer , Haim Horovitz , Robert Shaw , Sameer Pendharkar , Wen-Hwa Chu , Paul Mannas
发明人： Lily Springer , Haim Horovitz , Robert Shaw , Sameer Pendharkar , Wen-Hwa Chu , Paul Mannas
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage dependent design rule is applied to an edge of an area of the layout if the edge is not covered by a pseudo layer. A second voltage dependent design rule is, on the other hand, applied to the edge of the area if the edge is covered by the pseudo layer.
摘要翻译：公开了所提出的半导体设计布局中的至少一些的验证。根据本发明的一个或多个方面，如果边缘未被伪层覆盖，则将第一电压依赖设计规则应用于布局区域的边缘。另一方面，如果边缘被伪层覆盖，则第二电压依赖设计规则被应用于该区域的边缘。

4. 发明申请

US20070214441A1 Isolated pwell tank verification using node breakers 有权
标题翻译：使用节点断路器进行隔离池验证
公开(公告)号：US20070214441A1
公开(公告)日：2007-09-13
申请号：US11374259
申请日：2006-03-13
申请人： Haim Horovitz , Mark Allenspach , Peter Fleischmann
发明人： Haim Horovitz , Mark Allenspach , Peter Fleischmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A technique for checking a layout design of an integrated circuit is disclosed. The technique has application to converting the design of a circuit from schematic to layout form. Instances where multiple pwell isolation tanks are coupled to the same node and where one or more pwell isolation tanks are shorted to a substrate are detected. Node breakers are inserted in the layout between pwell isolation tanks coupled to the same node and between the substrate and isolated pwell tanks coupled to the substrate. The node breakers are inserted in the circuit schematic as well to satisfy a layout versus schematic comparison. Inserting the node breakers highlights circuit component groupings as well as which tanks contain certain elements, if any. This allows designers to make a conscious decision as to the location and groupings of elements in a layout design.
摘要翻译：公开了一种用于检查集成电路的布局设计的技术。该技术具有将电路设计从原理图转换为布局形式的应用。检测到多个孔隔离槽耦合到同一节点并且其中一个或多个孔隔离槽与基板短接的实例。节点断路器插入在连接到同一节点的隔离隔离槽之间以及耦合到基板的基板和隔离的储池之间的布局中。节点断路器也插入到电路原理图中，以满足布局与原理图比较。插入节点断路器突出显示电路组件分组，以及哪些坦克包含某些元素（如果有）。这使得设计者能够对布局设计中元素的位置和分组做出有意识的决定。

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