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    • 4. 发明授权
    • Fast multiplication of floating point values and integer powers of two
    • 浮点数和二进制的整数幂的快速乘法
    • US06233595B1
    • 2001-05-15
    • US09075074
    • 1998-05-08
    • Lei ChengFrank J. Gorishek, IVYi Liu
    • Lei ChengFrank J. Gorishek, IVYi Liu
    • G06F9302
    • G06F7/4876G06F9/30014
    • A method for performing fast multiplication in a microprocessor is disclosed. The method comprises detecting multiplication operations that have a floating point operand and an integer operand, wherein the integer operand is an integer power of two. Once detected, a multiplication operation meeting these criteria may be executed by using an integer adder to sum the integer power and the floating point operand's exponent to from a product exponent. The bias of the integer operand's exponent may also be subtracted. A product mantissa is simply copied from the floating point operand's mantissa. The floating point operand's sign bit may be inverted to form the product's sign bit if the integer operand is negative. Advantageously, the product is generated using integer addition which is faster than floating point multiplication. The method may be implemented in hardware or software.
    • 公开了一种在微处理器中执行快速乘法的方法。 该方法包括检测具有浮点操作数和整数操作数的乘法运算,其中整数操作数是2的整数幂。 一旦被检测到,可以通过使用整数加法器来执行满足这些标准的乘法运算,以从乘积指数将整数幂和浮点运算数的指数相加。 也可以减去整数操作数的指数的偏差。 产品尾数简单地从浮点运算符的尾数复制出来。 如果整数操作数为负,则浮点运算符的符号位可能会反转,以形成乘积符号位。 有利地,使用比浮点乘法更快的整数加法来产生乘积。 该方法可以在硬件或软件中实现。
    • 10. 发明授权
    • Method for testing the non-cacheable region functioning of a cache
memory controller
    • 用于测试缓存存储器控制器的非高速缓存区域功能的方法
    • US5974510A
    • 1999-10-26
    • US962361
    • 1997-10-31
    • Lei ChengThomas F. EckertMichael T. Wisor
    • Lei ChengThomas F. EckertMichael T. Wisor
    • G06F12/08G11C29/12
    • G06F12/0888G11C29/12
    • A method for testing the functioning of a non-cacheable region within a cache having a cache controller programmed with a write-back write policy and a non-cacheable region included in an image memory region corresponding to a physical memory region. A first data pattern is written to the cache tagged at a first addressable location of a cacheable region in the physical memory region. A second data pattern is written to the cache tagged at a second addressable location in the image memory region contained within both the non-cacheable region and the cacheable region and corresponding to the first addressable location. The data stored in the cache and tagged at the first addressable location and corresponding to the non-cacheable region only of the second addressable location is read to determine whether the first data pattern remains in the cache thereby indicating that the non-cacheable region is functioning correctly. The data stored and tagged at a third addressable location in the physical memory region and corresponding to the cacheable region only of the second addressable location in the image memory region is read to determine whether the second data pattern remains in the cache tagged at the third addressable location thereby indicating that the non-cacheable region is functioning correctly and that the memory size of the non-cacheable region is correct.
    • 一种用于测试具有由写回写入策略编程的高速缓存控制器和包含在对应于物理存储器区域的图像存储器区域中的不可缓存区域的高速缓存内的不可缓存区域的功能的方法。 将第一数据模式写入物理存储器区域中的可缓存区域的第一可寻址位置处标记的高速缓存。 将第二数据模式写入到包含在不可缓存区域和可高速缓存区域内并对应于第一可寻址位置的图像存储器区域中的第二可寻址位置处标记的高速缓存。 读取存储在高速缓存中并且在第一可寻址位置处标记并且仅对应于第二可寻址位置的不可缓存区域的数据,以确定第一数据模式是否保留在高速缓存中,从而指示不可缓存区域正在运行 正确的 在物理存储器区域中存储和标记在第三可寻址位置并且仅对应于图像存储器区域中的第二可寻址位置的可高速缓存区域的数据被读取以确定第二数据模式是否保留在第三可寻址的标记的高速缓存 位置,从而指示不可缓存区域正常工作,并且非可缓存区域的存储器大小是正确的。