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1. 发明申请

US20090077506A1 Simultaneous Multi-Layer Fill Generation 审中-公开
标题翻译：同时多层填充生成
公开(公告)号：US20090077506A1
公开(公告)日：2009-03-19
申请号：US12121135
申请日：2008-05-15
申请人： Eugene Anikin , Fedor Pikus , Laurence Grodd , David A. Abercrombie , John W. Stedman
发明人： Eugene Anikin , Fedor Pikus , Laurence Grodd , David A. Abercrombie , John W. Stedman
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G03F1/44 , G06F17/5045 , G06F17/5068 , G06F2217/12 , H01L27/0207 , Y02P90/265
摘要： Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.
摘要翻译：公开了用于优化电路层的电路布局设计中的图案密度的技术。分析电路设计中的层以定义可填充填充多边形（以下称为“填充”区域）的空区域。接下来，生成填充多边形的图案。在定义了填充多边形之后，层的布局设计被划分为单独的区域或“窗口”，并确定每个窗口的目标密度。一旦确定了该窗口的目标密度，则生成最接近该目标密度所需的填充多边形，并将其添加到电路布局设计中。该过程可以随着逐渐不同（例如较小的）填充多边形重复，直到每个窗口满足或超过规定的最小密度并且符合规定的最大密度梯度。此外，一些实施方案可允许用户通过向电路设计的多个层同时添加填充多边形来同时优化电路的多层密度。然后将多层填充结构的部分的表示添加到电路设计的相应层中，直到满足指定的目标密度。

2. 发明申请

US20060259978A1 Secure exchange of information in electronic design automation with license-related key generation 审中-公开
标题翻译：电子设计自动化中的信息安全交换与许可证相关的密钥生成
公开(公告)号：US20060259978A1
公开(公告)日：2006-11-16
申请号：US11393457
申请日：2006-03-29
申请人： Fedor Pikus , John Ferguson , Kyohei Sakajiri , Laurence Grodd
发明人： Fedor Pikus , John Ferguson , Kyohei Sakajiri , Laurence Grodd
IPC分类号： H04N7/16
CPC分类号： G06F17/5081 , H04L9/0833 , H04L9/0844 , H04L9/0866
摘要： Electronic data can be exchanged in a secure manner. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information can be processed without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool can be used to secure the information. A system can then unlock and use the secured information without revealing the same. In one desirable aspect, information can be encrypted or decrypted using a key, the key being generated based on licensing information associated with a software application.
摘要翻译：可以以安全的方式交换电子数据。被视为敏感而其他值得保护的信息可以通过加密，混淆和其他安全措施等方法来保护。可以处理安全信息，而不泄露至少一些安全信息。例如，可以选择性地注释与集成电路可制造性相关的规则文件，以指示其应得到保护的部分。可以使用加密工具来保护信息。然后，系统可以解锁和使用安全信息，而不会显示相同的信息。在一个理想的方面，可以使用密钥来加密或解密信息，所述密钥是基于与软件应用相关联的许可信息生成的。

3. 发明申请

US20060101428A1 Compressing integrated circuit design data files 审中-公开
标题翻译：压缩集成电路设计数据文件
公开(公告)号：US20060101428A1
公开(公告)日：2006-05-11
申请号：US11272201
申请日：2005-11-09
申请人： Anant Adke , Gilduin Barre , Laurence Grodd
发明人： Anant Adke , Gilduin Barre , Laurence Grodd
IPC分类号： G06F9/45
CPC分类号： G06F17/5045
摘要： Described herein are methods for generating concise descriptions of an IC layout. The description from a first format is read and deciphered for determining any patterns in any repetition of elements of an IC layout. The repetitions are then expressed in a concise form to further compress the description. Duplicative information can be avoided by the use of these methods and systems. The repetition patterns described include row-type and column-type patterns. Some selected element instances may be described as part of a random-type arrangement of element instances instead of being described individually.
摘要翻译：这里描述了用于产生IC布局的简明描述的方法。对来自第一格式的描述被读取和解密，以确定IC布局的元件的任何重复中的任何图案。然后以简洁的形式表达重复，以进一步压缩描述。可以通过使用这些方法和系统来避免重复的信息。所描述的重复模式包括行类型和列型模式。一些选择的元素实例可以被描述为元素实例的随机类型排列的一部分，而不是单独描述。

4. 发明申请

US20050234684A1 Design for manufacturability 审中-公开
公开(公告)号：US20050234684A1
公开(公告)日：2005-10-20
申请号：US10951710
申请日：2004-09-29
申请人： Joseph Sawicki , Laurence Grodd , John Ferguson , Sanjay Dhar
发明人： Joseph Sawicki , Laurence Grodd , John Ferguson , Sanjay Dhar
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5081 , G05B2219/35028 , G05B2219/45028 , G06F17/5045 , G06F2217/10 , G06F2217/12 , Y02P90/265
摘要： Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice.

5. 发明申请

US20050071659A1 Secure exchange of information in electronic design automation 有权
标题翻译：在电子设计自动化中安全交换信息
公开(公告)号：US20050071659A1
公开(公告)日：2005-03-31
申请号：US10895485
申请日：2004-07-20
申请人： John Ferguson , Fedor Pikus , Kyohei Sakajiri , Laurence Grodd
发明人： John Ferguson , Fedor Pikus , Kyohei Sakajiri , Laurence Grodd
IPC分类号： H04L9/08 , H04L9/30 , H04L9/00
CPC分类号： G06Q40/04 , H04L9/0838 , H04L2209/16
摘要： Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. For instance, the tool may be a physical verification tool capable of verifying whether any of the one or more integrated circuit layouts may violate one or more of the secured rules. An error report may be generated without revealing the secured rules.
摘要翻译：这里描述了用于安全地交换与电子设计自动化相关的信息的方法和系统。被视为敏感而其他值得保护的信息可以通过加密，混淆和其他安全措施等方法来保护。可以将安全信息提供给电子设计自动化工具用于处理，而不暴露至少一些安全信息。例如，可以选择性地注释与集成电路可制造性相关的规则文件，以指示其应得到保护的部分。可以使用加密工具来保护所指示的信息，并生成包括与电子设计自动化有关的安全信息的文件。然后，电子设计自动化工具可以解锁和使用安全信息，而不会泄露它们。例如，该工具可以是能够验证一个或多个集成电路布局中的任一个是否可能违反一个或多个安全规则的物理验证工具。可能会生成错误报告，而不会泄露安全规则。

6. 发明申请

US20060059443A1 Hierarchical feature extraction for electrical interaction 有权
标题翻译：电相互作用的分层特征提取
公开(公告)号：US20060059443A1
公开(公告)日：2006-03-16
申请号：US11202935
申请日：2005-08-12
申请人： Thomas Kauth , Patrick Gibson , Kurt Hertz , Laurence Grodd
发明人： Thomas Kauth , Patrick Gibson , Kurt Hertz , Laurence Grodd
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
摘要翻译：计算集成电路布局中的电路元件的电学相互作用的方法，而不使整个描述布局的数据库变平坦。在一个实施例中，分析分层数据库，并且在重复模式的每个实例处重新使用针对重复模式元素进行的电阻和电容计算，并根据局部条件进行调整。在另一个实施例中，将电路布局转换成多个瓦片，其中对瓦片的中心的电路元件和瓦片的边界区域进行的电阻和电容计算分别计算并组合。影响不同级别层次的电路元件之间的电气相互作用的环境信息是在较低级别的层次上进行计算，因此不需要对重复单元格的每个放置进行此类计算，因此不需要促进所有相互作用的元素到相同的层次级别来计算电相互作用。

7. 发明申请

US20050015740A1 Design for manufacturability 审中-公开
标题翻译：可制造性设计
公开(公告)号：US20050015740A1
公开(公告)日：2005-01-20
申请号：US10827990
申请日：2004-04-19
申请人： Joseph Sawicki , Laurence Grodd , John Ferguson , Sanjay Dhar
发明人： Joseph Sawicki , Laurence Grodd , John Ferguson , Sanjay Dhar
IPC分类号： G06F20060101 , G06F9/455 , G06F15/00 , G06F17/50
CPC分类号： G06F17/50 , G05B2219/35028 , G05B2219/45028 , G06F2217/12 , Y02P90/265
摘要： Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice.
摘要翻译：公开了用于修改现有微设计设计以提高其可制造性的技术。利用这些技术，设计者接收与设计中的数据相关的制造标准。然后，相关联的设计数据被识别并提供给微设计者，他们可以根据制造标准选择修改设计。以这种方式，设计人员可以直接在微型设备的原始设计中纳入铸造厂的制造标准。

8. 发明申请

US20050071792A1 Secure exchange of information in electronic design automation 有权
标题翻译：在电子设计自动化中安全交换信息
公开(公告)号：US20050071792A1
公开(公告)日：2005-03-31
申请号：US10920988
申请日：2004-08-17
申请人： John Ferguson , Fedor Pikus , Kyohei Sakajiri , Laurence Grodd
发明人： John Ferguson , Fedor Pikus , Kyohei Sakajiri , Laurence Grodd
IPC分类号： G06F20060101 , G06F9/45 , H04L9/08 , H04L9/30 , G06F17/50
CPC分类号： G06F21/6209 , G06F2221/2137
摘要： Information related to electronic design automation may be exchanged in a secure manner. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be processed without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. In one aspect, such access or secure use of the information may depend on one or more conditions being met (e.g., a time period or a number of uses or accesses). For instance, the tool may be a physical verification tool capable of verifying whether any of the one or more integrated circuit layouts may violate one or more of the secured rules.
摘要翻译：与电子设计自动化相关的信息可以以安全的方式交换。被视为敏感而其他值得保护的信息可以通过加密，混淆和其他安全措施等方法来保护。可以处理安全信息，而不泄露至少一些安全信息。例如，可以选择性地注释与集成电路可制造性相关的规则文件，以指示其应得到保护的部分。可以使用加密工具来保护与电子设计自动化有关的信息。然后，电子设计自动化工具可以解锁和使用安全信息，而不会泄露它们。在一个方面，信息的这种访问或安全使用可以取决于满足的一个或多个条件（例如，一个时间段或多个使用或访问）。例如，该工具可以是能够验证一个或多个集成电路布局中的任一个是否可能违反一个或多个安全规则的物理验证工具。

9. 发明授权

US4868745A Data processing system and method for the direct and indirect execution of uniformly structured object types 失效
标题翻译：用于直接和间接执行均匀结构化对象类型的数据处理系统和方法
公开(公告)号：US4868745A
公开(公告)日：1989-09-19
申请号：US868978
申请日：1986-05-30
申请人： Charles M. Patton , Laurence Grodd , William C. Wickes
发明人： Charles M. Patton , Laurence Grodd , William C. Wickes
IPC分类号： G06F9/44 , G06F12/00
CPC分类号： G06F9/45508
摘要： In a data processing system, uniformly structured objects are indifferently mixed in object memory with object pointers. The objects address prologues of object execution sequences in memory. The object pointers address other objects. The objects are properly evaluated whether directly or indirectly addressed. An interpreter pointer selectively points to or addresses objects or object pointers.When an object is directly addressed by the interpreter pointer, the addressee of the object's addressee in memory is addressed which initiates the object execution sequence.When an object is indirectly addressed, the pointer addresses an object pointer. The object pointer addresses an object. The object's addressee in memory is addressed which initiates the object execution process.
摘要翻译：在数据处理系统中，均匀结构化的对象在对象存储器中与对象指针无差异地混合。对象处理内存中对象执行序列的序言。对象指针指向其他对象。对象是否被直接或间接寻址进行了适当的评估。解释器指针有选择地指向或寻址对象或对象指针。当一个对象被解释器指针直接寻址时，对象的收件人在存储器中的收件人被寻址，起始对象的执行顺序。当一个对象被间接寻址时，该指针寻址一个对象指针。对象指针寻址一个对象。存储器中的对象的收件人被寻址，启动对象执行过程。

10. 发明申请

US20080034332A1 Optimization Of Geometry Pattern Density 审中-公开
标题翻译：几何图案密度优化
公开(公告)号：US20080034332A1
公开(公告)日：2008-02-07
申请号：US11743116
申请日：2007-05-01
申请人： Eugene Anikin , Fedor Pikus , John Stedman , Laurence Grodd , David Abercrombie
发明人： Eugene Anikin , Fedor Pikus , John Stedman , Laurence Grodd , David Abercrombie
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Techniques are provided for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define fill regions that can be filled with fill polygons A pattern of fill polygons also is generated, to fill the fill regions. The layout design for the layer then is divided into separate areas or “windows,” and a target density for each window is determined. More particularly, each window is analyzed to determine a target density for the window that will satisfy specified density constraint values, such as a minimum density constraint, a maximum density constraint, or a maximum density gradient constraint. In some implementations, the target density will be the smallest density that will comply with each of the specified density value constraints. Once the target density for the window has been determined, the fill polygons required to most closely approach this target density are selected and added to the circuit layout design. With some implementations, this process may be repeated for fill polygons of different sizes or shapes.
摘要翻译：提供了用于优化电路层的电路布局设计中的图案密度的技术。分析电路设计中的层，以定义可填充填充多边形的填充区域。还生成填充多边形的图案，以填充填充区域。然后将层的布局设计分为单独的区域或“窗口”，并确定每个窗口的目标密度。更具体地，分析每个窗口以确定将满足指定密度约束值（例如最小密度约束，最大密度约束或最大密度梯度约束）的窗口的目标密度。在一些实施方式中，目标密度将是符合每个特定密度值约束的最小密度。一旦确定了窗口的目标密度，则选择最接近该目标密度所需的填充多边形并将其添加到电路布局设计中。对于一些实现，对于不同大小或形状的填充多边形，可以重复该过程。

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