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1. 发明申请

WO2011059842A2 TECHNIQUES FOR PHASE DETECTION 审中-公开
标题翻译：相位检测技术
公开(公告)号：WO2011059842A2
公开(公告)日：2011-05-19
申请号：PCT/US2010/054900
申请日：2010-10-31
申请人： RAMBUS INC. , LEIBOWITZ, Brian , LEE, Hae-Chang , ARYANFAR, Farshid , CHANG, Kun-Yung , SHEN, Jie
发明人： LEIBOWITZ, Brian , LEE, Hae-Chang , ARYANFAR, Farshid , CHANG, Kun-Yung , SHEN, Jie
CPC分类号： H03D13/00 , H03L7/08 , H03L7/0814 , H03L7/0816 , H03L7/085
摘要： A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.
摘要翻译：相位检测电路可以包括两个相位检测器，每个相位检测器响应于输入信号的相位对齐而生成非零输出。输入信号基于两个周期性信号。当周期信号同相时，相位检测电路从另一相位检测器的输出信号中减去一个相位检测器的输出信号，以产生具有零值的信号。或者，相位检测器产生指示周期性信号之间的相位差的相位比较信号。响应于相位检测器的输入信号被同相对准，相位比较信号具有非零值。输入信号基于周期性信号。输出电路接收相位比较信号并且响应于周期性信号的相位对准而产生具有零值的输出。

2. 发明申请

WO2010129873A3 DRIVE SUPPORTING MULTIPLE SIGNALING MODES 审中-公开
标题翻译：驱动支持多种信号模式
公开(公告)号：WO2010129873A3
公开(公告)日：2011-02-03
申请号：PCT/US2010034047
申请日：2010-05-07
申请人： RAMBUS INC , CHANG KEN KUN-YUNG , PRABHU KASHINATH , LEE HAE-CHANG
发明人： CHANG KEN KUN-YUNG , PRABHU KASHINATH , LEE HAE-CHANG
IPC分类号： H03K19/0175 , H03K17/687
CPC分类号： H03K19/018585 , H03K19/018528
摘要： A driver supports differential and single-ended signaling modes. Complementary transistors with a common tail node are provided with complementary input signals in the differential mode. A current source coupled to the tail node maintains a relatively high tail impedance and a constant tail current in the differential mode. The tail node is set to a low impedance in single-ended modes to decouple the two transistors, allowing them to amplify uncorrelated input signals. The current source draws multiple current levels in the single- ended mode to compensate for changes in tail current that result from changes in the relative values of the uncorrelated data in the single-ended modes. A termination block provides termination resistance in the differential mode, pull-up transistors in a single-ended mode that employs push-pull drivers, and is omitted in a single-ended mode that lacks driver-side termination.
摘要翻译：驱动程序支持差分和单端信令模式。具有公共尾节点的互补晶体管在差分模式下被提供有互补输入信号。耦合到尾部节点的电流源在差分模式下保持相对高的尾部阻抗和恒定的尾部电流。尾端节点在单端模式下设置为低阻抗，以对两个晶体管进行去耦，从而使它们能够放大不相关的输入信号。电流源在单端模式下绘制多个电流电平，以补偿由单端模式中不相关数据的相对值变化引起的尾电流变化。端接模块提供差分模式下的终端电阻，采用推挽驱动器的单端模式的上拉晶体管，并且在缺少驱动器侧端接的单端模式下省略。

3. 发明申请

WO2010129873A2 DRIVE SUPPORTING MULTIPLE SIGNALING MODES 审中-公开
标题翻译：驱动支持多种信号模式
公开(公告)号：WO2010129873A2
公开(公告)日：2010-11-11
申请号：PCT/US2010/034047
申请日：2010-05-07
申请人： RAMBUS INC. , CHANG, Ken, Kun-Yung , PRABHU, Kashinath , LEE, Hae-Chang
发明人： CHANG, Ken, Kun-Yung , PRABHU, Kashinath , LEE, Hae-Chang
IPC分类号： H03K19/0175 , H03K17/687
CPC分类号： H03K19/018585 , H03K19/018528
摘要： A driver supports differential and single-ended signaling modes. Complementary transistors with a common tail node are provided with complementary input signals in the differential mode. A current source coupled to the tail node maintains a relatively high tail impedance and a constant tail current in the differential mode. The tail node is set to a low impedance in single-ended modes to decouple the two transistors, allowing them to amplify uncorrelated input signals. The current source draws multiple current levels in the single- ended mode to compensate for changes in tail current that result from changes in the relative values of the uncorrelated data in the single-ended modes. A termination block provides termination resistance in the differential mode, pull-up transistors in a single-ended mode that employs push-pull drivers, and is omitted in a single-ended mode that lacks driver-side termination.
摘要翻译：驱动程序支持差分和单端信令模式。具有公共尾节点的互补晶体管在差分模式下被提供有互补输入信号。耦合到尾节点的电流源在差分模式下保持相对较高的尾部阻抗和恒定的尾部电流。尾端节点在单端模式下设置为低阻抗，以对两个晶体管进行去耦，从而使它们能够放大不相关的输入信号。电流源在单端模式下吸收多个电流电平，以补偿由单端模式中不相关数据的相对值变化引起的尾电流变化。端接模块提供差分模式下的终端电阻，采用推挽驱动器的单端模式的上拉晶体管，并且在缺少驱动器侧端接的单端模式下被省略。

4. 发明申请

WO2009067386A1 BIDIRECTIONAL MEMORY INTERFACE WITH GLITCH TOLERANT BIT SLICE CIRCUITS 审中-公开
标题翻译：双向存储器接口，带有宽容比特片电路
公开(公告)号：WO2009067386A1
公开(公告)日：2009-05-28
申请号：PCT/US2008/083626
申请日：2008-11-14
申请人： RAMBUS INC. , CHANG, Kun-Yung , SHEN, Jie , LEE, Hae-Chang , ASSADERAGHI, Fariborz , PEREGO, Richard, E. , CHUN, Jung-Hoon
发明人： CHANG, Kun-Yung , SHEN, Jie , LEE, Hae-Chang , ASSADERAGHI, Fariborz , PEREGO, Richard, E. , CHUN, Jung-Hoon
IPC分类号： G06F13/16
CPC分类号： G06F13/1689
摘要： A bit slice circuit having transmit and receive modes of operation is described. The bit slice circuit comprises: first transmit circuitry and first receive circuitry operating in a first clock domain, wherein the first circuitry receives a first clock signal; second transmit circuitry and second receive circuitry operating in a second clock domain, wherein the second circuitry receives a second clock signal; transmit transition circuitry and receive transition circuitry, the transmit transition circuitry coupling the first transmit circuitry to the second transmit circuitry, the receive transition circuitry coupling the first receive circuitry to the second receive circuitry, wherein the transition circuitry receives the first and second clock signals; and a single phase mixer that generates the second clock signal, wherein the second clock signal has a first phase in the transmit mode of operation and second phase in the receive mode of operation.
摘要翻译：描述了具有发送和接收操作模式的位分片电路。所述位片电路包括：第一发射电路和在第一时钟域中操作的第一接收电路，其中所述第一电路接收第一时钟信号; 第二发送电路和在第二时钟域中操作的第二接收电路，其中所述第二电路接收第二时钟信号; 发射转换电路和接收转换电路，所述发射转换电路将所述第一发射电路耦合到所述第二发射电路，所述接收转换电路将所述第一接收电路耦合到所述第二接收电路，其中所述转换电路接收所述第一和第二时钟信号; 以及产生所述第二时钟信号的单相混频器，其中所述第二时钟信号具有所述发送操作模式中的第一相位和所述接收操作模式中的第二相位。

5. 发明申请

WO2008070138A9 METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN TRANSCEIVER DEVICES 审中-公开
标题翻译：收发器设备之间信道均衡不对称分布的方法和电路
公开(公告)号：WO2008070138A9
公开(公告)日：2009-03-05
申请号：PCT/US2007024948
申请日：2007-12-05
申请人： RAMBUS INC , ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
发明人： ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
IPC分类号： H04L25/03
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane (120-125) that extends between a high-performance integrated circuit (IC) (105) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers (110). The. architecture compensates for performance asymmetry between ICs communicating over a bidirectional lan by instantiating relatively complex transmit (Tx1) and receive (Rx1) equalization cir.cuitry on the higher-performance, side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated (162) based upon the signal response at the receiver of the higher-performance IC (Rx1N).
摘要翻译：收发机体系结构支持在高性能集成电路（IC）（105）和采用较不复杂的发射机和接收机（110）的一个或多个相对低性能的IC之间延伸的信号通道（120-125）上的高速通信。。的。通过在更高性能的通道侧实例化相对复杂的发送（Tx1）和接收（Rx1）均衡电路，体系结构补偿了通过双向lan进行通信的IC之间的性能不对称。基于在更高性能IC（Rx1N）的接收机处的信号响应，高性能IC中的发射和接收均衡滤波器系数都可以自适应地更新（162）。

6. 发明申请

WO2008070138A3 METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN TRANSCEIVER DEVICES 审中-公开
标题翻译：收发器之间通道均衡化的不对称分配方法与电路
公开(公告)号：WO2008070138A3
公开(公告)日：2009-01-15
申请号：PCT/US2007024948
申请日：2007-12-05
申请人： RAMBUS INC , ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
发明人： ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
IPC分类号： H04L25/03
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane (120-125) that extends between a high-performance integrated circuit (IC) (105) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers (110). The. architecture compensates for performance asymmetry between ICs communicating over a bidirectional lan by instantiating relatively complex transmit (Tx1) and receive (Rx1) equalization cir.cuitry on the higher-performance, side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated (162) based upon the signal response at the receiver of the higher-performance IC (Rx1N).
摘要翻译：收发器架构支持在高性能集成电路（IC）（105）和使用较不复杂的发送器和接收器（110）的一个或多个相对低性能的IC之间延伸的信号通道（120-125）上的高速通信，。的。架构通过在车道的较高性能侧实例化相对复杂的发送（Tx1）和接收（Rx1）均衡电路来补偿通过双向LAN通信的IC之间的性能不对称性。基于在高性能IC（Rx1N）的接收机处的信号响应，可以自适应地更新（162）高性能IC中的发射和接收均衡滤波器系数。

7. 发明申请

WO2009003129A2 METHODS AND CIRCUITS FOR ADAPTIVE EQUALIZATION AND CHANNEL CHARACTERIZATION USING LIVE DATA 审中-公开
标题翻译：使用实时数据的自适应均衡和通道特征的方法和电路
公开(公告)号：WO2009003129A2
公开(公告)日：2008-12-31
申请号：PCT/US2008/068409
申请日：2008-06-26
申请人： RAMBUS INC. , LEE, Hae-Chang , REN, Jihong , LEIBOWITZ, Brian S. , MADDEN, Christopher J. , LIN, Qi , ZERBE, Jared L.
发明人： LEE, Hae-Chang , REN, Jihong , LEIBOWITZ, Brian S. , MADDEN, Christopher J. , LIN, Qi , ZERBE, Jared L.
IPC分类号： H04L25/02 , H04L25/03 , H04L1/20
CPC分类号： H04L25/03878 , H04L1/203 , H04L1/205 , H04L25/0224 , H04L25/0242 , H04L25/0264 , H04L25/0272 , H04L25/03012 , H04L25/03343
摘要： A communication system supports high-speed communication over a signal lane that extends between respective transmitting and receiving integrated circuit (IC) devices. One or both of the IC devices includes an equalizer to offset channel characteristics that otherwise impair speed performance. A margining circuit on the receiving IC measures a timing margin of the received signal and adjusts the equalization settings for one or both transmitters to maximize the timing margin. Another embodiment compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex error analysis and adaptation circuitry on the higher-performance side of the lane. The error analysis and adaptation circuitry reduces the error margin of the transmitted signal to introduce bit errors at the receiver, analyzes the bit errors to measure ISI imposed by the channel, and adjusts voltage offsets of the continuous-time signal to compensate for the ISI. In some embodiments the receiver calculates the system response for diagnostics and for computing equalization settings.
摘要翻译：通信系统支持在相应的发射和接收集成电路（IC）设备之间延伸的信号通道上的高速通信。一个或两个IC器件包括均衡器以抵消否则会影响速度性能的通道特性。接收IC上的边缘电路测量接收信号的定时裕度，并调整一个或两个发射机的均衡设置以使定时裕度最大化。另一个实施例通过在车道的较高性能侧实例化相对复杂的误差分析和适配电路来补偿通过双向通道通信的IC之间的性能不对称性。误差分析和自适应电路减少发射信号的误差容限，在接收机引入位错误，分析比特误差以测量信道施加的ISI，并调整连续时间信号的电压补偿以补偿ISI。在一些实施例中，接收机计算用于诊断和计算均衡设置的系统响应。

8. 发明申请

WO2008085964A3 ADAPTIVE CONTINUOUS-TIME LINE EQUALIZER FOR CORRECTING THE FIRST POST-CURSOR ISI 审中-公开
公开(公告)号：WO2008085964A3
公开(公告)日：2008-07-17
申请号：PCT/US2008/000249
申请日：2008-01-07
申请人： RAMBUS INC. , LEE, Hae-Chang , LEIBOWITZ, Brian, S. , KIZER, Jade, M. , GREER III, Thomas, H. , BANSAL, Akash
发明人： LEE, Hae-Chang , LEIBOWITZ, Brian, S. , KIZER, Jade, M. , GREER III, Thomas, H. , BANSAL, Akash
IPC分类号： H04L25/03
摘要： A receiver includes a continuous-time equalizer (120), a decision-feedback equalizer (DFE) (125), data and error sampling logic (130), and an adaptation engine (135). The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

9. 发明申请

WO2011046845A3 SIGNAL DISTRIBUTION NETWORKS AND RELATED METHODS 审中-公开
标题翻译：信号分配网络及相关方法
公开(公告)号：WO2011046845A3
公开(公告)日：2011-08-18
申请号：PCT/US2010052115
申请日：2010-10-09
申请人： RAMBUS INC , ARYANFAR FARSHID , LEE HAE-CHANG , CHANG KUN-YUNG , WU TING , WERNER CARL , KOOCHAKZADEH MASOUD
发明人： ARYANFAR FARSHID , LEE HAE-CHANG , CHANG KUN-YUNG , WU TING , WERNER CARL , KOOCHAKZADEH MASOUD
IPC分类号： H04L12/02
CPC分类号： H03L7/093 , G06F1/10 , H03L7/0802
摘要： A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit.
摘要翻译：信号分配网络具有每个段具有缓冲电路，耦合到缓冲电路的传输线，通过传输线耦合到缓冲电路的电感器，以及耦合到电感器的可变电容电路，并通过传输线。可变电容电路的电容被设定为确定通过传输线传输的信号的相位和幅度。信号分配网络可以包括相位检测器，环路滤波器电路和谐振延迟电路。相位检测器将第一周期信号的相位与第二周期信号的相位进行比较。谐振延迟电路具有可变阻抗电路，其具有基于环路滤波器电路的输出信号的变化而变化的阻抗。

10. 发明申请

WO2011090767A2 PHASE DETECTION CIRCUITS AND METHODS 审中-公开
标题翻译：相位检测电路及方法
公开(公告)号：WO2011090767A2
公开(公告)日：2011-07-28
申请号：PCT/US2010/062615
申请日：2010-12-30
申请人： RAMBUS INC. , ARYANFAR, Farshid , LEE, Hae-Chang , WERNER, Carl
发明人： ARYANFAR, Farshid , LEE, Hae-Chang , WERNER, Carl
IPC分类号： H03L7/085
CPC分类号： H03L7/085 , G01R25/00 , H03D13/00 , H03L7/0816
摘要： A phase detector circuit compares the phases of first and second periodic input signals to generate an output signal. The phase detector includes a circuit that makes two different combinations of the first and the second periodic input signals to generate third and fourth periodic signals. This circuit causes the third periodic signal to be based on a first combination of the first periodic signal and the second periodic signal that imparts a first relative phase shift. The circuit causes the fourth periodic signal to be based on a second combination of the first periodic signal and the second periodic signal to provide a different relative phase shift. The phase detector also includes a comparison circuit that compares a measure of the power of the third periodic signal to a measure of the power of the fourth periodic signal to generate the phase comparison output signal.
摘要翻译：相位检测器电路比较第一和第二周期性输入信号的相位以产生输出信号。相位检测器包括使第一和第二周期性输入信号的两个不同组合产生第三和第四周期信号的电路。该电路使得第三周期信号基于第一周期信号和施加第一相对相移的第二周期信号的第一组合。电路使得第四周期信号基于第一周期信号和第二周期信号的第二组合，以提供不同的相对相移。相位检测器还包括比较电路，其将第三周期信号的功率的测量与第四周期信号的功率的测量进行比较，以产生相位比较输出信号。

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