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1. 发明申请

US20150294705A1 ELECTRONIC DEVICE 有权
标题翻译：电子设备
公开(公告)号：US20150294705A1
公开(公告)日：2015-10-15
申请号：US14563690
申请日：2014-12-08
申请人： Ji-Wang LEE , Dong-Keun KIM , Masahiro TAKAHASHI , Tsuneo INABA
发明人： Ji-Wang LEE , Dong-Keun KIM , Masahiro TAKAHASHI , Tsuneo INABA
IPC分类号： G11C11/16 , G11C13/00
CPC分类号： G11C11/1673 , G11C11/15 , G11C11/16 , G11C11/1659 , G11C11/5607 , G11C11/5657 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C16/28 , G11C2013/0054 , G11C2213/79
摘要： A semiconductor memory unit includes first to Nth variable resistance elements each having different resistance values according to values stored therein, wherein N is a natural number equal to or greater than 2; a reference resistance element having a first reference resistance value; and first to Nth comparison units which correspond to the first to Nth variable resistance elements, respectively, and each of which determines whether a resistance value of the corresponding variable resistance element is greater or less than a second reference resistance value, wherein the first to Nth comparison units are commonly coupled to the reference resistance element.
摘要翻译：半导体存储单元包括根据存储在其中的值具有不同电阻值的第一至第N可变电阻元件，其中N是等于或大于2的自然数; 具有第一参考电阻值的参考电阻元件; 以及分别对应于第一至第N可变电阻元件的第一至第N比较单元，并且每个比较单元确定相应的可变电阻元件的电阻值是否大于或小于第二参考电阻值，其中第一至第N 比较单元通常耦合到参考电阻元件。

2. 发明授权

US09054680B2 Methods of controlling clocks in system on chip including function blocks, systems on chips and semiconductor systems including the same 有权
公开(公告)号：US09054680B2
公开(公告)日：2015-06-09
申请号：US14559131
申请日：2014-12-03
申请人： Dong Keun Kim , Sun Cheol Kwon , Si Young Kim , Jae Gon Lee , Jung Hun Heo
发明人： Dong Keun Kim , Sun Cheol Kwon , Si Young Kim , Jae Gon Lee , Jung Hun Heo
IPC分类号： H03K3/00 , H03K5/04
CPC分类号： H03K5/04 , G06F1/08 , G06F1/324 , H03K19/0016 , H03K21/00 , H03K21/10 , Y02D10/126 , Y02D50/20
摘要： A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

3. 发明授权

US08139415B2 Phase-change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US08139415B2
公开(公告)日：2012-03-20
申请号：US12488637
申请日：2009-06-22
申请人： Dong-Keun Kim
发明人： Dong-Keun Kim
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C8/14 , G11C13/0004
摘要： A phase-change memory device is capable of reducing current consumption and preventing performance deterioration caused due to line load by improving a process of selecting memory cells for a write/read operation. The phase-change memory device has a plurality of cell matrixes and includes word line decoding units that are each shared by a plurality of cell matrixes arranged in a row direction and are configured to activate one of global row signals according to a first row address, local row switch units that are provided to the respective cell matrixes and are configured to connect local current lines to corresponding word lines in response to the activated global row signal, bus connecting units that are provided to the respective cell matrixes and are configured to connect the local current lines to global current lines, and enabling units configured to activate one of the global current lines according to a second row address.
摘要翻译：相变存储器件能够通过改善对写入/读取操作选择存储单元的处理来降低电流消耗并防止由于线路负载引起的性能劣化。相变存储器件具有多个单元矩阵，并且包括字线解码单元，每个字线解码单元由行行方向排列的多个单元矩阵共享，并且被配置为根据第一行地址激活全局行信号之一，本地行开关单元，其被提供给相应的单元矩阵，并且被配置为响应于激活的全局行信号将局部当前行连接到对应的字线，提供给相应的单元矩阵的总线连接单元被配置为将局部当前线路到全局当前线路，以及启用被配置为根据第二行地址激活全局当前线路之一的单元。

4. 发明申请

US20120051127A1 SYSTEM FOR HANDLING DATA IN A SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：用于在半导体存储器中处理数据的系统
公开(公告)号：US20120051127A1
公开(公告)日：2012-03-01
申请号：US12982996
申请日：2010-12-31
申请人： Tae Hun YOON , Dong Keun KIM
发明人： Tae Hun YOON , Dong Keun KIM
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0071
摘要： A semiconductor memory apparatus includes a memory cell, a data transfer unit configured to adjust an access to the memory cell according to a voltage level of a selection signal, a selection signal output unit configured to output the selection signal having a first control voltage level in a data write mode and a second control voltage level in a data read mode. A data detection unit may also be configured to detect a voltage formed by a sensing current supplied to the memory cell through the data transfer unit in the data read mode, and output read data according to the detection result, wherein the second control voltage level is lower than the first control voltage level.
摘要翻译：一种半导体存储装置，包括存储单元，数据传送单元，被配置为根据选择信号的电压来调整对存储单元的访问;选择信号输出单元，被配置为输出具有第一控制电压电平的选择信号数据写入模式和第二控制电压电平。数据检测单元还可以被配置为在数据读取模式中检测通过数据传送单元提供给存储单元的感测电流形成的电压，并且根据检测结果输出读取数据，其中第二控制电压电平为低于第一控制电压电平。

5. 发明申请

US20120051126A1 SEMICONDUCTOR MEMORY APPARATUS AND DATA READING METHOD THEREOF 有权
标题翻译：半导体存储器和数据读取方法
公开(公告)号：US20120051126A1
公开(公告)日：2012-03-01
申请号：US12982983
申请日：2010-12-31
申请人： Hyun Joo LEE , Dong Keun KIM
发明人： Hyun Joo LEE , Dong Keun KIM
IPC分类号： G11C11/21
CPC分类号： G11C13/004 , G11C13/0002 , G11C13/0004
摘要： A semiconductor memory apparatus includes: a read current supply unit configured to supply a read current; a resistive memory cell configured to pass a current having a magnitude corresponding to a resistance value thereof in a data read mode; a voltage transfer unit coupled between the read current supply unit and the resistive memory cell and configured to transfer the read current to the resistive memory cell, wherein a voltage corresponding to the magnitude of the passed current is formed at a sensing node; and a feedback unit configured to pull-down drive a connection node, which is coupled between the voltage transfer unit and the resistive memory cell, when a voltage level of the sensing node reaches a predefined level.
摘要翻译：半导体存储装置包括：读电流供给单元，被配置为提供读电流; 电阻存储单元，被配置为在数据读取模式中传递具有对应于其电阻值的幅度的电流; 耦合在读取电流供应单元和电阻式存储单元之间并被配置为将读取的电流传送到电阻式存储单元的电压转移单元，其中在感测节点处形成对应于所通过的电流的大小的电压; 以及反馈单元，被配置为当感测节点的电压电平达到预定水平时，下拉驱动耦合在电压传输单元和电阻存储器单元之间的连接节点。

6. 发明申请

US20110205789A1 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US20110205789A1
公开(公告)日：2011-08-25
申请号：US12844712
申请日：2010-07-27
申请人： Dong Keun KIM
发明人： Dong Keun KIM
IPC分类号： G11C11/00
CPC分类号： G11C7/18 , G11C13/0004 , G11C13/0023
摘要： A semiconductor memory apparatus includes a plurality of unit cell arrays having a plurality of word lines which are disposed in a row direction and a plurality of global bit lines which are disposed in a column direction; a row decoder configured to activate at least two word lines among the plurality of word lines in response to a row address which designates one word line; a global column switch block configured to select two different global bit lines among the plurality of global bit lines in response to column control signals; and a column decoder configured to generate the column control signals in response to a column address.
摘要翻译：一种半导体存储装置，具有：多个单元阵列，具有排列成行方向的多个字线和沿列方向配置的多个全局位线; 行解码器，其被配置为响应于指定一个字线的行地址来激活所述多个字线中的至少两个字线; 全局列切换块，被配置为响应于列控制信号选择多个全局位线中的两个不同的全局位线; 以及列解码器，被配置为响应于列地址而生成列控制信号。

7. 发明申请

US20110075474A1 PHASE CHANGE RANDOM ACCESS MEMORY APPARATUS AND WRITE CONTROL METHOD FOR THE SAME 有权
标题翻译：相位改变随机存取存储器和写入控制方法
公开(公告)号：US20110075474A1
公开(公告)日：2011-03-31
申请号：US12649086
申请日：2009-12-29
申请人： Dong Keun KIM
发明人： Dong Keun KIM
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C13/0061 , G11C13/0069 , G11C16/102
摘要： The disclosed phase change random access memory apparatus is configured to program a predetermined phase change memory cell in the phase change memory apparatus in response to a plurality of write instructions applied at independent points of time.
摘要翻译：所公开的相变随机存取存储装置被配置为响应于在独立时间点施加的多个写指令来对相变存储装置中的预定相变存储单元进行编程。

8. 发明申请

US20100227435A1 Chemical-mechanical polishing method for polishing phase-change material and method of fabricating phase-change memory device using the same 有权
标题翻译：用于研磨相变材料的化学机械抛光方法及使用其制造相变存储器件的方法
公开(公告)号：US20100227435A1
公开(公告)日：2010-09-09
申请号：US12591006
申请日：2009-11-04
申请人： Joon-sang Park , Chung-ki Min , Dong-keun Kim , Yeol Jon , Chang-sun Hwang , Tae-eun Kim
发明人： Joon-sang Park , Chung-ki Min , Dong-keun Kim , Yeol Jon , Chang-sun Hwang , Tae-eun Kim
IPC分类号： H01L21/06 , H01L21/306
CPC分类号： B24B37/015 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A chemical-mechanical polishing (CMP) method of polishing a phase-change material and a method of fabricating a phase-change memory, the CMP method including forming the phase-change material on an activation surface of a semiconductor wafer, and performing a CMP process on the phase-change material using a polishing pad, wherein the performing the CMP process includes reducing a change in the composition of the phase-change material by adjusting, within a predetermined range, a temperature of a region where the semiconductor wafer and the polishing pad contact each other.
摘要翻译：用于研磨相变材料的化学机械抛光（CMP）方法和制造相变存储器的方法，所述CMP方法包括在半导体晶片的活化表面上形成相变材料，并执行CMP 使用抛光垫对相变材料进行处理，其中执行CMP处理包括通过在预定范围内调节半导体晶片和第二晶体管的区域的温度来减小相变材料的组成的变化抛光垫彼此接触。

9. 发明申请

US20090303825A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20090303825A1
公开(公告)日：2009-12-10
申请号：US12347547
申请日：2008-12-31
申请人： Dong-Keun KIM , Jee-Eun Lee
发明人： Dong-Keun KIM , Jee-Eun Lee
IPC分类号： G11C8/00 , G11C8/08
CPC分类号： G11C8/12 , G11C11/4096 , G11C11/4097
摘要： A semiconductor memory device includes a first plurality of banks arranged in a first direction to form a first group of banks; a second plurality of banks arranged in the first direction to form a second group of banks, the first group of banks and the second group of banks arranged in a second direction; a first local data line arranged in the second direction to cross a bank of the second plurality of banks and to transfer input/output data; a second local data line arranged in the second direction to transfer input/output data; a global data line disposed in the first direction that crosses the second direction; and a data exchanger disposed between the second plurality of banks and the global data line for configured to controlling data exchange between the first and second local data lines and the global data line.
摘要翻译：半导体存储器件包括沿第一方向布置的第一组银，以形成第一组堤; 排列在所述第一方向上的第二组银，以形成第二组银行，所述第一组银行和所述第二组银行沿第二方向布置; 布置在所述第二方向上的第一本地数据线，以跨越所述第二多个存储体的存储体并传送输入/输出数据; 沿第二方向布置的用于传送输入/输出数据的第二本地数据线; 设置在与第二方向相交的第一方向上的全局数据线; 以及设置在第二多个存储体之间的数据交换器和全局数据线，用于配置为控制第一和第二本地数据线与全局数据线之间的数据交换。

10. 发明申请

US20090251983A1 SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF REDUCING GROUND NOISE 有权
标题翻译：可减少接地噪声的半导体存储器
公开(公告)号：US20090251983A1
公开(公告)日：2009-10-08
申请号：US12359606
申请日：2009-01-26
申请人： Dong Keun Kim , Chae Kyu Jang
发明人： Dong Keun Kim , Chae Kyu Jang
IPC分类号： G11C5/14 , G11C8/00 , G11C7/00
CPC分类号： G11C5/14 , G11C7/02
摘要： An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each of the first driving signal driving units such that a predetermined time difference is generated between an enable timing of the first driving signal and an enable timing of the second driving signal, a plurality of sense amplifier driving units, each of which generates a first driving level and a second driving level according to the first driving signal and the second driving signal, and a plurality of sense amplifiers that are provided for respective bit line pairs, and each include first type switching elements operating according to the first driving level and second type switching elements operating according to the second driving level.
摘要翻译：一种装置包括多个第一驱动信号驱动单元，并且通过驱动输入信号产生第一驱动信号;多个第二驱动信号驱动单元，其驱动输入信号并产生第二驱动信号;定时控制控制每个第一驱动信号驱动单元的单元，使得在第一驱动信号的使能定时和第二驱动信号的使能定时之间产生预定时间差;多个读出放大器驱动单元，其生成根据第一驱动信号和第二驱动信号的第一驱动电平和第二驱动电平以及针对各个位线对设置的多个读出放大器，并且各自包括根据第一驱动电平工作的第一类型的开关元件以及根据第二驱动电平工作的第二类型的开关元件。

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