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1. 发明授权

US08722530B2 Method of making a die with recessed aluminum die pads 有权
标题翻译：用凹槽铝模片制作模具的方法
公开(公告)号：US08722530B2
公开(公告)日：2014-05-13
申请号：US13192976
申请日：2011-07-28
申请人： Gregory S. Spencer , Phillip E. Crabtree , Dean J. Denning , Kurt H. Junker , Gerald A. Martin
发明人： Gregory S. Spencer , Phillip E. Crabtree , Dean J. Denning , Kurt H. Junker , Gerald A. Martin
IPC分类号： H01L23/48 , H01L33/62 , H01L21/768 , H01L23/488
CPC分类号： H01L21/76879 , H01L21/31053 , H01L21/31056 , H01L21/76804 , H01L21/76885 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/0345 , H01L2224/0362 , H01L2224/0391 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/05567 , H01L2224/05572 , H01L2224/05582 , H01L2224/05624 , H01L2224/05681 , H01L2224/05686 , H01L2924/00014 , H01L2924/1305 , H01L2924/1461 , H01L2924/00012 , H01L2924/04941 , H01L2924/01029 , H01L2924/00 , H01L2224/05552
摘要： A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.
摘要翻译：制造半导体器件的方法包括形成电互连层，在互连层上形成第一介电层，在互连层的第一电互连上在第一介电层中形成开口，在第一电介质上形成铝层蚀刻所述铝层以形成铝管芯焊盘，在所述铝管芯焊盘和所述第一介电层上形成第二电介质层，以及通过所述第一和第二电介质层形成导电通孔以接触所述互连的第二电互连层。

2. 发明授权

US07579228B2 Disposable organic spacers 有权
标题翻译：一次性有机垫片
公开(公告)号：US07579228B2
公开(公告)日：2009-08-25
申请号：US11825953
申请日：2007-07-10
申请人： Paul A. Grudowski , Kurt H. Junker , Thomas J. Kropewnicki , Andrew G. Nagy
发明人： Paul A. Grudowski , Kurt H. Junker , Thomas J. Kropewnicki , Andrew G. Nagy
IPC分类号： H01L21/8238
CPC分类号： H01L21/823468 , H01L21/02115 , H01L21/02274 , H01L21/31122 , H01L21/31138 , H01L21/312 , H01L21/3146 , H01L21/823864 , H01L29/6653 , Y10S438/943
摘要： A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (210); (b) forming a first set of organic spacers (213) adjacent to said first electrode; (c) depositing a first photo mask (215) over the structure; and (d) simultaneously removing the first set of organic spacers and the first photo mask.
摘要翻译：提供一种制造半导体器件的方法，包括（a）提供包括第一栅电极（210）的半导体结构; （b）形成与所述第一电极相邻的第一组有机间隔物（213）; （c）在所述结构上沉积第一光掩模（215）; 和（d）同时去除第一组有机间隔物和第一光掩模。

3. 发明申请

US20090017587A1 Disposable organic spacers 有权
公开(公告)号：US20090017587A1
公开(公告)日：2009-01-15
申请号：US11825953
申请日：2007-07-10
申请人： Paul A. Grudowski , Kurt H. Junker , Thomas J. Kropewnicki , Andrew G. Nagy
发明人： Paul A. Grudowski , Kurt H. Junker , Thomas J. Kropewnicki , Andrew G. Nagy
IPC分类号： H01L21/8238
CPC分类号： H01L21/823468 , H01L21/02115 , H01L21/02274 , H01L21/31122 , H01L21/31138 , H01L21/312 , H01L21/3146 , H01L21/823864 , H01L29/6653 , Y10S438/943
摘要： A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (210); (b) forming a first set of organic spacers (213) adjacent to said first electrode; (c) depositing a first photo mask (215) over the structure; and (d) simultaneously removing the first set of organic spacers and the first photo mask.

4. 发明申请

US20080220617A1 Deep STI trench and SOI undercut enabling STI oxide stressor 失效
标题翻译：深STI沟槽和SOI底切使STI氧化应激反应
公开(公告)号：US20080220617A1
公开(公告)日：2008-09-11
申请号：US11716058
申请日：2007-03-07
申请人： Michael D. Turner , Suresh Venkatesan , Kurt H. Junker
发明人： Michael D. Turner , Suresh Venkatesan , Kurt H. Junker
IPC分类号： H01L21/31
CPC分类号： H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/66772 , H01L29/78 , H01L29/7846 , H01L29/78654
摘要： A method for imparting stress to the channel region of a transistor is provided. In accordance with the method, a semiconductor layer (307) is provided which has a dielectric layer (305) disposed beneath it. A trench (319) is created which extends through the semiconductor layer and into the dielectric layer, and the trench is backfilled with a stressor material (320), thereby forming a trench isolation structure. A channel region (326) is defined in the semiconductor layer adjacent to the trench isolation structure.
摘要翻译：提供了向晶体管的沟道区域施加应力的方法。根据该方法，提供半导体层（307），其具有设置在其下方的电介质层（305）。产生一个延伸穿过半导体层并进入电介质层的沟槽（319），沟槽用应力源材料（320）回填，从而形成沟槽隔离结构。在与沟槽隔离结构相邻的半导体层中限定沟道区（326）。

5. 发明申请

US20080173908A1 Multilayer silicon nitride deposition for a semiconductor device 审中-公开
标题翻译：用于半导体器件的多层氮化硅沉积
公开(公告)号：US20080173908A1
公开(公告)日：2008-07-24
申请号：US11655461
申请日：2007-01-19
申请人： Kurt H. Junker , Paul A. Grudowski , Xiang-Zheng Bo , Tien Ying Luo
发明人： Kurt H. Junker , Paul A. Grudowski , Xiang-Zheng Bo , Tien Ying Luo
IPC分类号： H01L29/78 , H01L21/3105 , H01L21/8238
CPC分类号： H01L21/02348 , H01L21/0217 , H01L21/02274 , H01L21/02351 , H01L21/3105 , H01L21/3185 , H01L21/823807 , H01L29/7843
摘要： A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (131) of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (133) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.
摘要翻译：提供了制造半导体器件的方法，其包括（a）提供配备有栅极和沟道区域的半导体结构，所述沟道区域与栅极相关联; （b）在半导体结构上沉积第一应力源材料的第一子层（131），所述第一应力源材料含有硅 - 氮键并向半导体结构施加拉伸应力; （c）通过暴露于辐射源固化第一应激物材料; （d）在所述第一子层上沉积第二应力源材料的第二子层（133），所述第二应力源材料含有硅 - 氮键并向所述半导体结构施加拉伸应力; 和（e）通过暴露于辐射源固化应力源材料的第二子层。

6. 发明授权

US06972255B2 Semiconductor device having an organic anti-reflective coating (ARC) and method therefor 有权
标题翻译：具有有机抗反射涂层（ARC）的半导体器件及其方法
公开(公告)号：US06972255B2
公开(公告)日：2005-12-06
申请号：US10628668
申请日：2003-07-28
申请人： Douglas M. Reber , Mark D. Hall , Kurt H. Junker , Kyle W. Patterson , Tab Allen Stephens , Edward K. Theiss , Srikanteswara Dakshiina-Murthy , Marilyn Irene Wright
发明人： Douglas M. Reber , Mark D. Hall , Kurt H. Junker , Kyle W. Patterson , Tab Allen Stephens , Edward K. Theiss , Srikanteswara Dakshiina-Murthy , Marilyn Irene Wright
IPC分类号： H01L21/027 , H01L21/033 , H01L21/28 , H01L21/3213 , H01L21/44
CPC分类号： H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/0332 , H01L21/0338 , H01L21/28035 , H01L21/28123 , H01L21/31612 , H01L21/32139 , H01L29/6659 , H01L29/7833 , Y10S438/902 , Y10S438/952
摘要： In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.
摘要翻译：在制造半导体器件中，待蚀刻的导电材料上方的图案化叠层具有图案化的光致抗蚀剂层，其用于对四乙基原硅酸盐（TEOS）层进行图案化。在比常规温度低的温度下沉积TEOS层。低温TEOS层位于导电层上方的有机抗反射涂层（ARC）上。低温TEOS层提供有机ARC和光致抗蚀剂之间的粘附，具有低缺陷性，作为硬掩模操作，并且用作与有机ARC组合有助于减少不期望的反射的相移层。

7. 发明授权

US07799678B2 Method for forming a through silicon via layout 有权
标题翻译：通过布局形成通硅的方法
公开(公告)号：US07799678B2
公开(公告)日：2010-09-21
申请号：US12022195
申请日：2008-01-30
申请人： Thomas J. Kropewnicki , Ritwik Chatterjee , Kurt H. Junker
发明人： Thomas J. Kropewnicki , Ritwik Chatterjee , Kurt H. Junker
IPC分类号： H01L21/44
CPC分类号： H01L21/76898
摘要： A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields.
摘要翻译：用于形成TSV布局的方法减少了由于通过具有固有拉伸应力或中性应力的氮化硅层形成TSV引起的氮化硅层中的凹陷。在一个实施例中，该方法包括通过将TSV位置移动到本征拉伸应力的区域来补偿拉伸应力氮化硅层，或者通过在TSV区域中替换压缩应力的氮化硅层。压缩应力的氮化硅层在TSV蚀刻工艺期间比拉伸应力下的氮化硅层经历较少的凹陷。当将电介质衬垫施加到TSV的侧壁时，更小的凹陷更容易填充，从而减少形成空隙的可能性。此外，较小的凹槽需要更小的排除区域，导致用于TSV的集成电路的较小表面积以及更高的可靠性和更高的产量。

8. 发明申请

US20090191708A1 METHOD FOR FORMING A THROUGH SILICON VIA LAYOUT 有权
标题翻译：通过布局形成通过硅的方法
公开(公告)号：US20090191708A1
公开(公告)日：2009-07-30
申请号：US12022195
申请日：2008-01-30
申请人： Thomas J. Kropewnicki , Ritwik Chatterjee , Kurt H. Junker
发明人： Thomas J. Kropewnicki , Ritwik Chatterjee , Kurt H. Junker
IPC分类号： H01L21/768
CPC分类号： H01L21/76898
摘要： A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields.
摘要翻译：用于形成TSV布局的方法减少了由于通过具有固有拉伸应力或中性应力的氮化硅层形成TSV引起的氮化硅层中的凹陷。在一个实施例中，该方法包括通过将TSV位置移动到本征拉伸应力的区域来补偿拉伸应力氮化硅层，或者通过在TSV区域中替换压缩应力的氮化硅层。压缩应力的氮化硅层在TSV蚀刻工艺期间比拉伸应力下的氮化硅层经历较少的凹陷。当将电介质衬垫施加到TSV的侧壁时，更小的凹陷更容易填充，从而减少形成空隙的可能性。此外，较小的凹槽需要更小的排除区域，导致用于TSV的集成电路的较小表面积以及更高的可靠性和更高的产量。

9. 发明申请

US20080272411A1 SEMICONDUCTOR DEVICE WITH MULTIPLE TENSILE STRESSOR LAYERS AND METHOD 有权
标题翻译：具有多个拉伸压力层的半导体器件和方法
公开(公告)号：US20080272411A1
公开(公告)日：2008-11-06
申请号：US11744581
申请日：2007-05-04
申请人： Xiangzheng Bo , Tien Ying Luo , Kurt H. Junker , Paul A. Grudowski , Venkat R. Kolagunta
发明人： Xiangzheng Bo , Tien Ying Luo , Kurt H. Junker , Paul A. Grudowski , Venkat R. Kolagunta
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/7843 , H01L21/268 , H01L21/3105 , H01L21/3185 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.
摘要翻译：半导体器件具有至少两个用UV辐射固化的拉伸应力层。在第一应力层之后形成第二拉伸应力层。在一些实例中，拉伸应力层包括氮化硅和氢。在一些实例中，第二拉伸应力层由于固化而比第一拉伸应力层具有更大的收缩率。在一种形式中，固化后的第二拉伸应力层比第一拉伸应力层具有更大的拉伸应力。拉伸应力层用于改善N沟道晶体管中的载流子迁移率，从而提高晶体管性能。在一种形式中，提供单组上覆的拉伸应力层，每层越来越厚，并且在固化之前具有越来越多的氢。在其它实施方案中，形成多个重叠的基团，每个基团具有相似的重复深度和氢分布。

10. 发明授权

US07176130B2 Plasma treatment for surface of semiconductor device 失效
标题翻译：半导体器件表面等离子体处理
公开(公告)号：US07176130B2
公开(公告)日：2007-02-13
申请号：US10987790
申请日：2004-11-12
申请人： Jin Miao Shen , Brian J. Fisher , Mark D. Hall , Kurt H. Junker , Vikas R. Sheth , Mehul D. Shroff
发明人： Jin Miao Shen , Brian J. Fisher , Mark D. Hall , Kurt H. Junker , Vikas R. Sheth , Mehul D. Shroff
IPC分类号： H01L21/441
CPC分类号： H01L21/32139 , H01L21/02164 , H01L21/02274 , H01L21/0234 , H01L21/0276 , H01L21/3105 , H01L21/31612
摘要： A method for forming a semiconductor device (10) includes forming an organic anti-reflective coating (OARC) layer (18) over the semiconductor device (10). A tetra-ethyl-ortho-silicate (TEOS) layer (20) is formed over the OARC layer (18). The TEOS layer (20) is exposed to oxygen-based plasma at a temperature of at most about 300 degrees Celsius. In an alternative embodiment, the TEOS layer (20) is first exposed to a nitrogen-based plasma before being exposed to the oxygen-based plasma. A photoresist layer (22) is formed over the TEOS layer (20) and patterned. By applying oxygen based plasma and nitrogen based plasma to the TEOS layer (20) before applying photoresist, pattern defects are reduced.
摘要翻译：一种用于形成半导体器件（10）的方法包括在半导体器件（10）上形成有机抗反射涂层（OARC）层（18）。在OARC层（18）上形成四乙基原硅酸盐（TEOS）层（20）。 TEOS层（20）在至多约300摄氏度的温度下暴露于基于氧的等离子体。在替代实施例中，首先将TEOS层（20）暴露于基于氧的等离子体之前的氮基等离子体。光致抗蚀剂层（22）形成在TEOS层（20）上并被图案化。在施加光致抗蚀剂之前，通过将氧基等离子体和氮基等离子体施加到TEOS层（20）上，减少了图案缺陷。

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