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1. 发明申请

US20060199341A1 Methods of forming threshold voltage implant regions 失效
标题翻译：形成阈值电压注入区域的方法
公开(公告)号：US20060199341A1
公开(公告)日：2006-09-07
申请号：US11406893
申请日：2006-04-18
申请人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

2. 发明申请

US20060183291A1 Methods of forming capacitor structures 失效
公开(公告)号：US20060183291A1
公开(公告)日：2006-08-17
申请号：US11406862
申请日：2006-04-18
申请人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
IPC分类号： H01L21/425
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

3. 发明授权

US06194738B1 Method and apparatus for storage of test results within an integrated circuit 失效
标题翻译：在集成电路内存储测试结果的方法和装置
公开(公告)号：US06194738B1
公开(公告)日：2001-02-27
申请号：US09032417
申请日：1998-02-27
申请人： Brett Debenham , Kim Pierce , Douglas J. Cutter , Kurt Beigel , Fan Ho , Patrick J. Mullarkey , Dien Luong , Hua Zheng , Michael Shore , Jeffrey P. Wright , Adrian E. Ong , Todd A. Merritt
发明人： Brett Debenham , Kim Pierce , Douglas J. Cutter , Kurt Beigel , Fan Ho , Patrick J. Mullarkey , Dien Luong , Hua Zheng , Michael Shore , Jeffrey P. Wright , Adrian E. Ong , Todd A. Merritt
IPC分类号： H01L2358
CPC分类号： H01L27/112 , G01R31/31702 , G01R31/3181 , G11C17/10 , G11C17/18
摘要： An integrated circuit memory device has a plurality of nonvolatile programmable elements which are used to store a pass/fail status bit at selected milestones in a test sequence. At selected points in the test process an element may be programmed to indicate that the device has passed the tests associated with the selected point in the process. Prior to performing further tests on the device, the element is read to verify that it passed previous tests in the test process. If the appropriate elements are not programmed, the device is rejected. A rejected device may be retested according to the previous test steps. Laser fuses, electrically programmable fuses or antifuses are used to store test results. The use of electrically writeable nonvolatile memory elements allows for programming of the elements after the device has been packaged.
摘要翻译：集成电路存储器件具有多个非易失性可编程元件，用于在测试序列中存储所选择的里程碑处的通过/失败状态位。在测试过程的选定点，元件可以被编程以指示设备已经通过与该过程中的所选点相关联的测试。在对设备执行进一步测试之前，读取该元素以验证其在测试过程中通过先前的测试。如果没有编写适当的元素，则设备被拒绝。可以根据先前的测试步骤重新测试被拒绝的设备。激光熔丝，电可编程熔丝或反熔丝用于存储测试结果。使用电可写非易失性存储器元件允许在器件被封装之后对元件进行编程。

4. 发明申请

US20060198179A1 MULTI-RESISTIVE INTEGRATED CIRCUIT MEMORY 有权
标题翻译：多电阻集成电路存储器
公开(公告)号：US20060198179A1
公开(公告)日：2006-09-07
申请号：US11379441
申请日：2006-04-20
申请人： R. Baker , Kurt Beigel
发明人： R. Baker , Kurt Beigel
IPC分类号： G11C11/22
CPC分类号： H01L28/82 , G11C5/04 , G11C11/15 , H01L23/5223 , H01L27/0214 , H01L27/0805 , H01L2924/0002 , Y10S257/905 , Y10S257/906 , Y10S257/908 , H01L2924/00
摘要： A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.
摘要翻译：用于集成电路的电容器包括一层导电材料。所述导电材料层包括至少第一部分和第二部分，其中所述第一部分和所述第二部分相对于彼此以预定图案布置，以提供每半导体管芯面积的最大量的电容。

5. 发明申请

US20050026387A1 Bulk-isolated PN diode and method of forming a bulk-isolated PN diode 有权
标题翻译：大容量隔离PN二极管和形成大容量隔离PN二极管的方法
公开(公告)号：US20050026387A1
公开(公告)日：2005-02-03
申请号：US10930512
申请日：2004-08-31
申请人： Kurt Beigel
发明人： Kurt Beigel
IPC分类号： H01L27/06 , H01L27/08 , H01L29/417 , H01L29/861 , H01L21/8234
CPC分类号： H01L27/0814 , H01L27/0629 , H01L29/417 , H01L29/861
摘要： A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of MOSFET diode-connected transistors. In addition, a method for manufacturing the bulk isolated PN diodes is recited.
摘要翻译：制造大容量隔离PN二极管的技术。具体地，提供了一种用一对体隔离PN二极管制造电压钳的技术。另一个实施例提供了具有一对体耦合的PN二极管与一对MOSFET二极管连接的晶体管并联的电压钳位。此外，还列举了用于制造体分离PN二极管的方法。

6. 发明授权

US06365421B2 Method and apparatus for storage of test results within an integrated circuit 失效
标题翻译：在集成电路内存储测试结果的方法和装置
公开(公告)号：US06365421B2
公开(公告)日：2002-04-02
申请号：US09531023
申请日：2000-03-20
申请人： Brett Debenham , Kim Pierce , Douglas J. Cutter , Kurt Beigel , Fan Ho , Patrick J. Mullarkey , Dien Luong , Hua Zheng , Michael Shore , Jeffrey P. Wright , Adrian E. Ong , Todd A. Merritt
发明人： Brett Debenham , Kim Pierce , Douglas J. Cutter , Kurt Beigel , Fan Ho , Patrick J. Mullarkey , Dien Luong , Hua Zheng , Michael Shore , Jeffrey P. Wright , Adrian E. Ong , Todd A. Merritt
IPC分类号： H01L2166
CPC分类号： H01L27/112 , G01R31/31702 , G01R31/3181 , G11C17/10 , G11C17/18
摘要： An integrated circuit memory device has a plurality of nonvolatile programmable elements which are used to store a pass/fail status bit at selected milestones in a test sequence. At selected points in the test process an element may be programmed to indicate that the device has passed the tests associated with the selected point in the process. Prior to performing further tests on the device, the element is read to verify that it passed previous tests in the test process. If the appropriate elements are not programmed, the device is rejected. A rejected device may be retested according to the previous test steps. Laser fuses, electrically programmable fuses or antifuses are used to store test results. The use of electrically writeable nonvolatile memory elements allows for programming of the elements after the device has been packaged.
摘要翻译：集成电路存储器件具有多个非易失性可编程元件，用于在测试序列中存储所选择的里程碑处的通过/失败状态位。在测试过程的选定点，元件可以被编程以指示设备已经通过与该过程中的所选点相关联的测试。在对设备执行进一步测试之前，读取该元素以验证其在测试过程中通过先前的测试。如果没有编写适当的元素，则设备被拒绝。可以根据先前的测试步骤重新测试被拒绝的设备。激光熔丝，电可编程熔丝或反熔丝用于存储测试结果。使用电可写非易失性存储器元件允许在器件被封装之后对元件进行编程。

7. 发明申请

US20060046381A1 Methods of forming capacitor structures, methods of forming threshold voltage implant regions, and methods of implanting dopant into channel regions 失效
标题翻译：形成电容器结构的方法，形成阈值电压注入区域的方法以及将掺杂剂注入沟道区域的方法
公开(公告)号：US20060046381A1
公开(公告)日：2006-03-02
申请号：US10925736
申请日：2004-08-24
申请人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

8. 发明申请

US20050280005A1 Bulk-isolated PN diode and method of forming a bulk-isolated PN diode 有权
公开(公告)号：US20050280005A1
公开(公告)日：2005-12-22
申请号：US11204462
申请日：2005-08-16
申请人： Kurt Beigel
发明人： Kurt Beigel
IPC分类号： H01L27/06 , H01L27/08 , H01L29/417 , H01L29/861 , H01L29/15
CPC分类号： H01L27/0814 , H01L27/0629 , H01L29/417 , H01L29/861
摘要： A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of MOSFET diode-connected transistors. In addition, a method for manufacturing the bulk isolated PN diodes is recited.

9. 发明申请

US20050219927A1 Method for stabilizing or offsetting voltage in an integrated circuit 审中-公开
公开(公告)号：US20050219927A1
公开(公告)日：2005-10-06
申请号：US11126015
申请日：2005-05-10
申请人： R. Baker , Kurt Beigel
发明人： R. Baker , Kurt Beigel
IPC分类号： G11C7/02 , H01L21/02 , H01L23/522 , H01L27/02 , H01L27/08
CPC分类号： H01L28/82 , G11C5/04 , G11C11/15 , H01L23/5223 , H01L27/0214 , H01L27/0805 , H01L2924/0002 , Y10S257/905 , Y10S257/906 , Y10S257/908 , H01L2924/00
摘要： A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.

10. 发明申请

US20060199340A1 Methods of implanting dopant into channel regions 有权
标题翻译：将掺杂剂注入通道区域的方法
公开(公告)号：US20060199340A1
公开(公告)日：2006-09-07
申请号：US11406863
申请日：2006-04-18
申请人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

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