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1. 发明专利

JP2006244198A Effective sales system for cargo compartment space of aircraft 审中-公开
标题翻译：飞机货柜空间的有效销售系统
公开(公告)号：JP2006244198A
公开(公告)日：2006-09-14
申请号：JP2005060020
申请日：2005-03-04
申请人： Osamu Uno , 修宇野
发明人： UNO OSAMU
IPC分类号： G06Q30/06 , G06Q30/08 , G06Q50/00 , G06Q50/30
摘要： PROBLEM TO BE SOLVED: To effectively use a space, to reduce a transportation cost of a consigner and to improve an income of an airline and a fowarder, by merchandizing an unused space of a cargo compartment space in an aircraft to be sold, and by selling a loading-secured space by auction. SOLUTION: A user can use an unused space buying-in and selling system and an auction sales system for the loading-secured space, when accessing a home page 40 of a net carrier via a user terminal 20. A server 10 is provided to attain it with a main system such as an airline unused space sales control part 14 and a loading-secured space auction contract control part 21, and a related system. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了有效利用空间，通过销售要销售的飞机上的货舱空间的未使用空间来降低发货人的运输成本并提高航空公司和货主的收入，并通过拍卖出售装货保障空间。解决方案：当经由用户终端20访问网络运营商的主页40时，用户可以使用未使用的空间购买和销售系统以及用于加载保护空间的拍卖销售系统。服务器10是提供用于通过诸如航空公司未使用空间销售控制部分14和装载保证空间拍卖合同控制部分21之类的主要系统以及相关系统来实现。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2006244196A Support system for managing international transportation risk 审中-公开
标题翻译：国际运输风险管理支持系统
公开(公告)号：JP2006244196A
公开(公告)日：2006-09-14
申请号：JP2005059998
申请日：2005-03-04
申请人： Osamu Uno , 修宇野
发明人： UNO OSAMU
IPC分类号： G06Q40/00 , G06Q40/04 , G06Q40/08 , G06Q50/00 , G06Q50/26 , G06Q50/28
摘要： PROBLEM TO BE SOLVED: To prevent a cargo accident by using a support system for managing an international transportation risk provided by risk consulting from a user, to manage the risk in a supply chain, to quickly solve a claim after occurrence of the accident, and to reduce a cost and a time concerned in a damage reparation activity. SOLUTION: All the risk management programs prepared by processes from (1) registration comprising mainly safety to (15) reconsideration of risk management in a conceptional schema of an international transportation risk management system shown in Fig. 2 and Fig. 3 (not shown) can be used when the user accesses a risk consulting home page 40 via a user terminal 20. The server 10 is provided to attain it with a main system such as a safe consigner data input support part 12, a check list preparation support part 22, a safety condition tracking service control part 27 and a claim treatment process control part, and a related system. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了通过使用支持系统来管理由用户的风险咨询提供的国际运输风险，管理供应链中的风险来防止货物事故，在发生供应链之后迅速解决索赔事故，并减少损害赔偿活动的费用和时间。
解决方案：图1所示的国际运输风险管理体系概念模式中所有由（1）注册组成的流程编制的所有风险管理计划，主要包括安全性，（15）重新考虑风险管理。 2，当用户经由用户终端20访问风险咨询主页40时，可以使用图3（未示出）。服务器10被提供以用诸如安全发货人数据输入支持部分12，检查列表等主系统来实现准备支撑部分22，安全条件跟踪服务控制部分27和索赔处理过程控制部分以及相关系统。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006155446A Consulting system for reducing logistics cost 审中-公开
标题翻译：用于降低物流成本的咨询系统
公开(公告)号：JP2006155446A
公开(公告)日：2006-06-15
申请号：JP2004348052
申请日：2004-12-01
申请人： Osamu Uno , 修宇野
发明人： UNO OSAMU
IPC分类号： G06Q10/00 , G06Q10/06 , G06Q30/06 , G06Q50/00 , G06Q50/28
摘要： PROBLEM TO BE SOLVED: To provide a consulting service for reducing logistics costs by presenting a user in advance with the amount by which the logistics costs can be reduced (before execution of initial diagnosis). SOLUTION: This consulting system includes a supply chain process competitiveness evaluating part 14 for evaluating and/or analyzing the existing logistics costs inputted from a user terminal, a supply chain process, and a list of management systems while referring to databases DB1, DB2, DB3, DB4; a management system competitiveness evaluating part 15; a fair charge/bill calculating part 13; and a reducible logistics cost calculating part 12 for calculating the reducible logistics costs based on these systems and providing a user with a summary sheet of reducible logistics costs. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一个用于降低物流成本的咨询服务，提前向用户提供可以减少物流成本的金额（在执行初始诊断之前）。解决方案：该咨询系统包括供应链流程竞争力评估部分14，用于评估和/或分析从用户终端输入的现有物流成本，供应链流程和管理系统列表，同时参考数据库DB1， DB2，DB3，DB4; 管理体系竞争力评估第15部分; 公平收费/票据计算部13; 以及可缩减的物流成本计算部分12，用于基于这些系统计算可缩减的物流成本，并向用户提供可降低物流成本的总结表。版权所有（C）2006，JPO＆NCIPI

4. 发明授权

US07342116B2 Process for producing heterocyclic aldehyde 有权
标题翻译：制备杂环醛的方法
公开(公告)号：US07342116B2
公开(公告)日：2008-03-11
申请号：US10509228
申请日：2003-03-25
申请人： Yasuhiro Shiomi , Osamu Uno , Akio Ohta , Takeshi Sunakami
发明人： Yasuhiro Shiomi , Osamu Uno , Akio Ohta , Takeshi Sunakami
IPC分类号： C07D211/70 , C07D333/22
CPC分类号： C07D213/48
摘要： A process is disclosed for preparing a heterocyclic aldehyde by oxidizing a heterocyclic alcohol with high selectivity and high yield. Specifically, the heterocyclic aldehyde is prepared by reacting a heterocyclic compound having at least one hydroxymethyl group bonded to a carbon atom of a heterocyclic ring with a hypohalogenous acid salt in the presence of a base to oxidize the hydroxymethyl group, wherein reaction is conducted in the co-presence of a 2,2,6,6-tetramethylpiperidine-1-oxyl derivative having at least two 2,2,6,6-tetramethylpiperidine-1-oxyl-4-yl groups.
摘要翻译：公开了通过以高选择性和高产率氧化杂环醇制备杂环醛的方法。具体地说，杂环醛通过在碱的存在下使具有至少一个羟基甲基与杂环的碳原子键合的杂环化合物与低级卤酸酸盐反应来制备，以氧化羟甲基，其中反应在具有至少两个2,2,6,6-四甲基哌啶-1-氧基-4-基的2,2,6,6-四甲基哌啶-1-氧基衍生物的共存。

5. 发明授权

US07414442B2 Buffer circuit and integrated circuit 失效
标题翻译：缓冲电路和集成电路
公开(公告)号：US07414442B2
公开(公告)日：2008-08-19
申请号：US11117383
申请日：2005-04-29
申请人： Osamu Uno
发明人： Osamu Uno
IPC分类号： H03K3/00
CPC分类号： H03K19/0013 , H03K17/22 , H03K17/223
摘要： In a two-stage inverter circuit including an inverter circuit constituted by first and second FETs and an inverter circuit constituted by two FETs, a source and a gate of a third FET are connected to a first power source and a second power source, respectively. A drain of the third FET is connected to a source of the first FET. A source and a gate of a fourth FET are connected to the first power source and the second power source, respectively. A drain of the fourth FET is connected to a source of a seventh FET. A gate of the seventh FET is connected to the second power source, and a drain of the seventh FET is connected to a back gates of the first, third, fourth, seventh and fifth FETs. The drain of the third FET is connected to the drain of the fourth FET.
摘要翻译：在包括由第一和第二FET构成的反相器电路的两级反相器电路和由两个FET构成的反相器电路中，第三FET的源极和栅极分别连接到第一电源和第二电源。第三FET的漏极连接到第一FET的源极。第四FET的源极和栅极分别连接到第一电源和第二电源。第四FET的漏极连接到第七FET的源极。第七FET的栅极连接到第二电源，第七FET的漏极连接到第一，第三，第四，第七和第五FET的背栅极。第三FET的漏极连接到第四FET的漏极。

6. 发明授权

US07208978B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07208978B2
公开(公告)日：2007-04-24
申请号：US11116358
申请日：2005-04-28
申请人： Osamu Uno
发明人： Osamu Uno
IPC分类号： H03K19/0175
CPC分类号： H03K19/00315 , H03K17/0822 , H03K17/102
摘要： In a semiconductor device in which an applying voltage higher than a power supply voltage VDD is inputted to a terminal BUS, when the voltage VBUS is less than a voltage of the power supply voltage VDD plus a threshold voltage Vthp, a voltage obtained by subtracting a threshold voltage Vthn from the power supply voltage VDD is applied to the gate terminal G4 and the PMOS transistor P4 becomes conductive. The power supply voltage VDD is supplied to the gate terminal G2 to turn the PMOS transistor P2 off. When the voltage VBUS is equal to or higher than the voltage of the power supply voltage VDD plus the threshold voltage Vthp, the voltage VBUS is supplied to the gate terminal G4 to turn the PMOS transistor P4 off, and the PMOS transistor P3 conducts and supplies the voltage VBUS to the gate terminal G2 to turn the PMOS transistor P4 off. The voltage level is correctly maintained without an undesirable leak current from the terminal BUS regardless of the applying voltage VBUS.
摘要翻译：在将高于电源电压VDD的施加电压输入到端子BUS的半导体装置中，当电压VBUS小于电源电压VDD的电压加上阈值电压Vthp时，通过减去来自电源电压VDD的阈值电压Vthn被施加到栅极端子G 4，并且PMOS晶体管P 4导通。电源电压VDD被提供给栅极端子G2以使PMOS晶体管P 2截止。当电压VBUS等于或高于电源电压VDD的电压加上阈值电压Vthp时，电压VBUS被提供给栅极端子G4以使PMOS晶体管P 4截止，并且PMOS晶体管P 3 导通并将电压VBUS提供给栅极端子G 2，以使PMOS晶体管P 4截止。无论施加电压VBUS如何，电压电平被正确地维持而没有来自端子总线的不期望的泄漏电流。

7. 发明申请

US20050189963A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050189963A1
公开(公告)日：2005-09-01
申请号：US11116358
申请日：2005-04-28
申请人： Osamu Uno
发明人： Osamu Uno
IPC分类号： H03K19/00 , H03K19/003 , H03K19/0175
CPC分类号： H03K19/00315 , H03K17/0822 , H03K17/102
摘要： In a semiconductor device in which an applying voltage higher than a power supply voltage VDD is inputted to a terminal BUS, when the voltage VBUS is less than a voltage of the power supply voltage VDD plus a threshold voltage Vthp, a voltage obtained by subtracting a threshold voltage Vthn from the power supply voltage VDD is applied to the gate terminal G4 and the PMOS transistor P4 becomes conductive. The power supply voltage VDD is supplied to the gate terminal G2 to turn the PMOS transistor P2 off. When the voltage VBUS is equal to or higher than the voltage of the power supply voltage VDD plus the threshold voltage Vthp, the voltage VBUS is supplied to the gate terminal G4 to turn the PMOS transistor P4 off, and the PMOS transistor P3 conducts and supplies the voltage VBUS to the gate terminal G2 to turn the PMOS transistor P4 off. The voltage level is correctly maintained without an undesirable leak current from the terminal BUS regardless of the applying voltage VBUS.
摘要翻译：在将高于电源电压VDD的施加电压输入到端子BUS的半导体装置中，当电压VBUS小于电源电压VDD的电压加上阈值电压Vthp时，通过减去来自电源电压VDD的阈值电压Vthn被施加到栅极端子G 4，并且PMOS晶体管P 4导通。电源电压VDD被提供给栅极端子G2以使PMOS晶体管P 2截止。当电压VBUS等于或高于电源电压VDD的电压加上阈值电压Vthp时，电压VBUS被提供给栅极端子G4以使PMOS晶体管P 4截止，并且PMOS晶体管P 3 导通并将电压VBUS提供给栅极端子G 2，以使PMOS晶体管P 4截止。无论施加电压VBUS如何，电压电平被正确地维持而没有来自端子总线的不期望的泄漏电流。

8. 发明授权

US06924669B2 Output buffer circuit and control method therefor 有权
标题翻译：输出缓冲电路及其控制方法
公开(公告)号：US06924669B2
公开(公告)日：2005-08-02
申请号：US09735555
申请日：2000-12-14
申请人： Kunihiro Itoh , Osamu Uno
发明人： Kunihiro Itoh , Osamu Uno
IPC分类号： H03K19/0185 , H03K17/16 , H03K19/003 , H03K19/094 , H03K19/0175
CPC分类号： H03K19/00361 , H03K17/167
摘要： An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.
摘要翻译：输出缓冲器包括接收具有尖锐波形的输入信号的第一驱动电路，并产生具有平缓波形的输出信号。第二驱动电路在输出端子处连接到第一驱动电路，并且具有比第一驱动电路低的阻抗。延迟电路也连接到输出端子并产生延迟的输出信号。第一控制电路连接在延迟电路和第二驱动电路之间，并接收输入信号和延迟的输出信号，并产生用于驱动第二驱动电路的第一控制信号。

9. 发明授权

US5129478A Seat occupant restraining device 失效
标题翻译：座椅约束装置
公开(公告)号：US5129478A
公开(公告)日：1992-07-14
申请号：US560564
申请日：1990-07-31
申请人： Koji Suenaga , Osamu Uno , Koji Hirose
发明人： Koji Suenaga , Osamu Uno , Koji Hirose
IPC分类号： B60R21/00 , B60R21/02
CPC分类号： B60R21/02 , B60R2021/0074 , B60R2021/022
摘要： A restraining device for limiting forward movement of an operator of a wheeled mechanical vehicle in case of a collision includes two restraining bars pivotally mounted at opposite sides of a seat and extending toward one another. The restraining bars are mounted so as to pivot in a vertical plane about axes which are parallel to each other and lie on opposite sides of the seat. The restraining bars are synchronized or interlocked so that when one bar is raised or lowered by the occupant of the seat the other bar is also moved. A lock or retention device on one side of the seat holds the restraining bars in the lowered or raised position after they have been positioned by the occupant. The vehicle may be a forklift or front end loader and the run controls and load controls of the vehicle are interlocked with the synchronizing mechanism so that the run and load controls cannot be operated when the restraining bars are not in the occupant restraining position.
摘要翻译：在碰撞的情况下，用于限制轮式机械车辆的操作者的向前运动的约束装置包括枢转地安装在座椅的相对侧并且彼此延伸的两个限制杆。约束杆安装成围绕彼此平行并位于座椅的相对侧上的轴线在垂直平面中枢转。限制杆是同步的或互锁的，使得当一个杆被座椅的乘员升高或降低时，另一个杆也移动。在座椅一侧的锁定或保持装置在被乘员定位之后将限制杆保持在降低或升高位置。车辆可以是叉车或前端装载机，并且车辆的行驶控制和负载控制与同步机构互锁，使得当限制杆不在乘员约束位置时，行驶和负载控制不能操作。

10. 发明申请

US20050189964A1 Output buffer circuit and control method therefor 有权
公开(公告)号：US20050189964A1
公开(公告)日：2005-09-01
申请号：US11121130
申请日：2005-05-04
申请人： Kunihiro Itoh , Osamu Uno
发明人： Kunihiro Itoh , Osamu Uno
IPC分类号： H03K19/0185 , H03K17/16 , H03K19/003 , H03K19/094
CPC分类号： H03K19/00361 , H03K17/167
摘要： An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.

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