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1. 发明申请

US20110180864A1 MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20110180864A1
公开(公告)日：2011-07-28
申请号：US12691964
申请日：2010-01-22
申请人： YU-FONG HUANG , Miao-Chih Hsu , Kuan-Fu Chen , Tzung-Ting Han
发明人： YU-FONG HUANG , Miao-Chih Hsu , Kuan-Fu Chen , Tzung-Ting Han
IPC分类号： H01L27/115 , H01L21/8246
CPC分类号： H01L27/11568 , H01L29/66833 , H01L29/7926
摘要： A memory device is provided, including a substrate, a conductive layer, a charge storage layer, a plurality of isolation structures, a plurality of first doped regions, and a plurality of second doped regions. The substrate has a plurality of trenches. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The isolation structures are disposed in the substrate between two adjacent trenches, respectively. The first doped regions are disposed in an upper portion of the substrate between each isolation structure and each trench, respectively. The second doped regions are disposed in the substrate under a bottom portion of the trenches, in which each isolation structure is disposed between two adjacent second doped regions.
摘要翻译：提供了一种存储器件，包括衬底，导电层，电荷存储层，多个隔离结构，多个第一掺杂区和多个第二掺杂区。衬底具有多个沟槽。导电层设置在基板上并填充沟槽。电荷存储层设置在基板和导电层之间。隔离结构分别设置在两个相邻沟槽之间的衬底中。第一掺杂区域分别设置在每个隔离结构和每个沟槽之间的衬底的上部。第二掺杂区域设置在沟槽的底部下方的衬底中，其中每个隔离结构设置在两个相邻的第二掺杂区域之间。

2. 发明授权

US07671278B2 Cable having EMI-suppressing arrangement and method for making the same 失效
标题翻译：具有EMI抑制布置的电缆及其制造方法
公开(公告)号：US07671278B2
公开(公告)日：2010-03-02
申请号：US11981287
申请日：2007-10-31
申请人： Jen-Guo Fong , Hsi-Fu Lee , Kuan-Fu Chen
发明人： Jen-Guo Fong , Hsi-Fu Lee , Kuan-Fu Chen
IPC分类号： H01B7/18
CPC分类号： H01B11/1083 , B05D1/02 , B05D1/265 , B05D7/58 , B05D2256/00 , B32B15/02
摘要： Provided herewith a cable (1, 2) with EMI suppressing arrangement which comprises a conductive wire (10) and an insulative layer (20) enveloping over the wire. A braided metal layer (30) envelops over the insulative layer, and a magnetic layer (40, 501) is arranged thereover. And an insulative jacket (50, 502) envelops over the magnetic layer.
摘要翻译：提供具有EMI抑制布置的电缆（1,2），其包括导线（10）和包围在导线上的绝缘层（20）。编织金属层（30）包围在绝缘层上方，并且在其上布置有磁性层（40,501）。并且绝缘套管（50,502）包围在磁性层上。

3. 发明申请

US20090116274A1 DIODE-LESS ARRAY FOR ONE-TIME PROGRAMMABLE MEMORY 有权
标题翻译：一次性可编程存储器的二极管阵列
公开(公告)号：US20090116274A1
公开(公告)日：2009-05-07
申请号：US12346706
申请日：2008-12-30
申请人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming-Shang Chen
发明人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming-Shang Chen
IPC分类号： G11C17/00 , H01L29/66
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.
摘要翻译：一次可编程存储器阵列包括在第一行方向上延伸并且设置在第一高度的第一行导体，在第二行方向上延伸并设置在第二高度的第二行导体和沿列方向延伸的列导体并且设置成与第一行导体相邻并且与第二行导体相邻。阵列还包括覆盖列导体的至少一部分的电介质层，耦合在列导体上的电介质层和第二行导体之间的熔丝链。

4. 发明授权

US07515158B2 Modularly configurable memory system for LCD TV system 有权
标题翻译：用于液晶电视系统的模块化可配置存储系统
公开(公告)号：US07515158B2
公开(公告)日：2009-04-07
申请号：US11158872
申请日：2005-06-22
申请人： Peter Chang , Kuan Fu Chen
发明人： Peter Chang , Kuan Fu Chen
IPC分类号： G06T1/60
CPC分类号： H04N21/44004 , G09G5/001 , G09G5/39 , G09G2360/12 , H04N19/423 , H04N21/42692 , H04N21/443
摘要： A configurable memory system provides a high bandwidth, low latency, no wait state data path to a memory system functioning as a frame buffer for a digital video processing system. The configurable memory system has configurable channels that are programmable to control the access pattern of the memory controller. Once the configurable channels are programmed, the memory controller can generate the necessary address, timing, and control signals for selectively writing the data to and reading the data from the selected blocks of the array of memory devices continuously access the memory and move the data to the channel buffers. The channel buffer receives, retains, and transfers a defined segment of the data as defined by the segment pattern between the processing system and the array of memory devices, such that the processing system is able to transfer and receive the data continuously according to data requirements of the processing system.
摘要翻译：可配置的存储器系统提供高带宽，低等待时间，无等待状态数据路径到用作数字视频处理系统的帧缓冲器的存储器系统。可配置存储器系统具有可编程的可配置通道，以控制存储器控制器的访问模式。一旦可配置的通道被编程，存储器控制器可以产生必要的地址，定时和控制信号，用于选择性地将数据写入存储器件阵列的所选块并从其中读取数据，并持续访问存储器并将数据移动到通道缓冲区。信道缓冲器接收，保留和传送由处理系统和存储器件阵列之间的段模式定义的数据的定义段，使得处理系统能够根据数据要求连续地传送和接收数据的处理系统。

5. 发明授权

US08552528B2 Diode-less array for one-time programmable memory 失效
公开(公告)号：US08552528B2
公开(公告)日：2013-10-08
申请号：US13240589
申请日：2011-09-22
申请人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming Shang Chen
发明人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming Shang Chen
IPC分类号： H01L23/52 , H01L29/40 , G11C5/06 , G11C17/00
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

6. 发明申请

US20120008363A1 Diode-Less Array for One-Time Programmable Memory 失效
标题翻译：一次性可编程存储器的二极管阵列
公开(公告)号：US20120008363A1
公开(公告)日：2012-01-12
申请号：US13240589
申请日：2011-09-22
申请人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming Shang Chen
发明人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming Shang Chen
IPC分类号： G11C17/16 , G11C17/00
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.
摘要翻译：一次可编程存储器阵列包括在第一行方向上延伸并且设置在第一高度的第一行导体，在第二行方向上延伸并设置在第二高度的第二行导体和沿列方向延伸的列导体并且设置成与第一行导体相邻并且与第二行导体相邻。阵列还包括覆盖列导体的至少一部分的电介质层，耦合在列导体上的电介质层和第二行导体之间的熔丝链。

7. 发明申请

US20110220986A1 MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20110220986A1
公开(公告)日：2011-09-15
申请号：US12724053
申请日：2010-03-15
申请人： Yu-Fong Huang , I-Shen Tsai , Shang-Wei Lin , Miao-Chih Hsu , Kuan-Fu Chen
发明人： Yu-Fong Huang , I-Shen Tsai , Shang-Wei Lin , Miao-Chih Hsu , Kuan-Fu Chen
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L27/11568
摘要： A memory device including a substrate, a conductive layer, a charge storage layer, first and second dopant regions and first and second cell dopant regions is provided. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first and second dopant regions having a first conductive type are configured in the substrate under bottoms of the trenches and in an upper portion of the substrate between two adjacent trenches, respectively. The first and second cell dopant regions having a second conductive type are configured in the substrate between lower portions of side surfaces of the trenches and in the substrate adjacent to the bottoms of the second dopant regions, respectively. The first and the second conductive types are different dopant types.
摘要翻译：提供了包括基板，导电层，电荷存储层，第一和第二掺杂剂区以及第一和第二单元掺杂区的存储器件。多个沟槽部署在基板中。导电层设置在基板上并填充沟槽。电荷存储层设置在基板和导电层之间。具有第一导电类型的第一和第二掺杂剂区域分别在沟槽的底部和衬底的上部分别配置在衬底中。具有第二导电类型的第一和第二单元掺杂区域分别配置在沟槽的侧表面的下部和与第二掺杂区的底部相邻的衬底中的衬底中。第一和第二导电类型是不同的掺杂剂类型。

8. 发明授权

US07486534B2 Diode-less array for one-time programmable memory 有权
标题翻译：一次可编程存储器的无二极管阵列
公开(公告)号：US07486534B2
公开(公告)日：2009-02-03
申请号：US11297529
申请日：2005-12-08
申请人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming Shang Chen
发明人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming Shang Chen
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.
摘要翻译：一次可编程存储器阵列包括在第一行方向上延伸并且设置在第一高度的第一行导体，在第二行方向上延伸并设置在第二高度的第二行导体和沿列方向延伸的列导体并且设置成与第一行导体相邻并且与第二行导体相邻。阵列还包括覆盖列导体的至少一部分的电介质层，耦合在列导体上的电介质层和第二行导体之间的熔丝链。

9. 发明授权

US08593850B2 Diode-less array for one-time programmable memory 有权
公开(公告)号：US08593850B2
公开(公告)日：2013-11-26
申请号：US12346706
申请日：2008-12-30
申请人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming-Shang Chen
发明人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming-Shang Chen
IPC分类号： G11C17/00 , G11C17/06 , G11C17/18
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

10. 发明授权

US08183106B2 Apparatus and associated method for making a floating gate memory device with buried diffusion dielectric structures and increased gate coupling ratio 有权
标题翻译：用于制造具有掩埋扩散电介质结构和增加的栅极耦合比的浮动栅极存储器件的装置和相关方法
公开(公告)号：US08183106B2
公开(公告)日：2012-05-22
申请号：US11460216
申请日：2006-07-26
申请人： Kuan Fu Chen , Yin Jen Chen , Meng Hsuan Weng , Tzung Ting Han , Ming Shang Chen , Chun Pei Wu
发明人： Kuan Fu Chen , Yin Jen Chen , Meng Hsuan Weng , Tzung Ting Han , Ming Shang Chen , Chun Pei Wu
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/8238
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.
摘要翻译：一种用于制造浮动栅极存储器件的方法包括使用自对准工艺在不需要附加光刻步骤的部分栅极结构上形成第四多晶硅层。因此，可以实现增强的器件可靠性，因为可以以较低的栅极偏置电平保持更高的GCR。此外，可以减少流程复杂性，从而增加吞吐量并减少设备故障。

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