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1. 发明申请

US20110220986A1 MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20110220986A1
公开(公告)日：2011-09-15
申请号：US12724053
申请日：2010-03-15
申请人： Yu-Fong Huang , I-Shen Tsai , Shang-Wei Lin , Miao-Chih Hsu , Kuan-Fu Chen
发明人： Yu-Fong Huang , I-Shen Tsai , Shang-Wei Lin , Miao-Chih Hsu , Kuan-Fu Chen
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L27/11568
摘要： A memory device including a substrate, a conductive layer, a charge storage layer, first and second dopant regions and first and second cell dopant regions is provided. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first and second dopant regions having a first conductive type are configured in the substrate under bottoms of the trenches and in an upper portion of the substrate between two adjacent trenches, respectively. The first and second cell dopant regions having a second conductive type are configured in the substrate between lower portions of side surfaces of the trenches and in the substrate adjacent to the bottoms of the second dopant regions, respectively. The first and the second conductive types are different dopant types.
摘要翻译：提供了包括基板，导电层，电荷存储层，第一和第二掺杂剂区以及第一和第二单元掺杂区的存储器件。多个沟槽部署在基板中。导电层设置在基板上并填充沟槽。电荷存储层设置在基板和导电层之间。具有第一导电类型的第一和第二掺杂剂区域分别在沟槽的底部和衬底的上部分别配置在衬底中。具有第二导电类型的第一和第二单元掺杂区域分别配置在沟槽的侧表面的下部和与第二掺杂区的底部相邻的衬底中的衬底中。第一和第二导电类型是不同的掺杂剂类型。

2. 发明授权

US08836004B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08836004B2
公开(公告)日：2014-09-16
申请号：US12724053
申请日：2010-03-15
申请人： Yu-Fong Huang , I-Shen Tsai , Shang-Wei Lin , Miao-Chih Hsu , Kuan-Fu Chen
发明人： Yu-Fong Huang , I-Shen Tsai , Shang-Wei Lin , Miao-Chih Hsu , Kuan-Fu Chen
IPC分类号： H01L29/76 , H01L27/115 , H01L29/792
CPC分类号： H01L29/792 , H01L27/11568
摘要： A memory device including a substrate, a conductive layer, a charge storage layer, first and second dopant regions and first and second cell dopant regions is provided. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first and second dopant regions having a first conductive type are configured in the substrate under bottoms of the trenches and in an upper portion of the substrate between two adjacent trenches, respectively. The first and second cell dopant regions having a second conductive type are configured in the substrate between lower portions of side surfaces of the trenches and in the substrate adjacent to the bottoms of the second dopant regions, respectively. The first and the second conductive types are different dopant types.
摘要翻译：提供了包括基板，导电层，电荷存储层，第一和第二掺杂剂区以及第一和第二单元掺杂区的存储器件。多个沟槽部署在基板中。导电层设置在基板上并填充沟槽。电荷存储层设置在基板和导电层之间。具有第一导电类型的第一和第二掺杂剂区域分别在沟槽的底部和衬底的上部分别配置在基板的两个相邻的沟槽之间。具有第二导电类型的第一和第二电池掺杂剂区域分别配置在沟槽的侧表面的下部和与第二掺杂剂区的底部相邻的衬底中的衬底中。第一和第二导电类型是不同的掺杂剂类型。

3. 发明申请

US20090091983A1 NON-VOLATILE MEMORY STRUCTURE AND ARRAY THEREOF 有权
标题翻译：非易失性存储器结构及其阵列
公开(公告)号：US20090091983A1
公开(公告)日：2009-04-09
申请号：US11866756
申请日：2007-10-03
申请人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
发明人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.
摘要翻译：提供了包括基板，堆叠图案和应力图案的非易失性存储器结构。层叠图案设置在基板上。每个堆叠图案包括电荷存储结构和从底部到顶部的栅极。这里，电荷存储结构至少包括电荷存储层。应力图案分别设置在两个相邻堆叠图案之间的基板上。

4. 发明授权

US08466508B2 Non-volatile memory structure including stress material between stacked patterns 有权
标题翻译：非易失性存储器结构，包括层叠图案之间的应力材料
公开(公告)号：US08466508B2
公开(公告)日：2013-06-18
申请号：US11866756
申请日：2007-10-03
申请人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
发明人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
IPC分类号： H01L29/792 , H01L29/788 , H01L21/762
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.
摘要翻译：提供了包括基板，堆叠图案和应力图案的非易失性存储器结构。层叠图案设置在基板上。每个堆叠图案包括电荷存储结构和从底部到顶部的栅极。这里，电荷存储结构至少包括电荷存储层。应力图案分别设置在两个相邻堆叠图案之间的基板上。

5. 发明申请

US20090213656A1 FLASH MEMORY HAVING INSULATING LINERS BETWEEN SOURCE/DRAIN LINES AND CHANNELS 有权
标题翻译：在源/排水管线和通道之间具有绝缘衬套的闪存
公开(公告)号：US20090213656A1
公开(公告)日：2009-08-27
申请号：US12038612
申请日：2008-02-27
申请人： Shaw Hung Ku , Teng Hao Yeh , Shih-Chin Lee , Shang-Wei Lin , Chia-Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
发明人： Shaw Hung Ku , Teng Hao Yeh , Shih-Chin Lee , Shang-Wei Lin , Chia-Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
IPC分类号： G11C11/34 , H01L21/8247
CPC分类号： H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.
摘要翻译：存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

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