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1. 发明授权

US07486534B2 Diode-less array for one-time programmable memory 有权
标题翻译：一次可编程存储器的无二极管阵列
公开(公告)号：US07486534B2
公开(公告)日：2009-02-03
申请号：US11297529
申请日：2005-12-08
申请人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming Shang Chen
发明人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming Shang Chen
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.
摘要翻译：一次可编程存储器阵列包括在第一行方向上延伸并且设置在第一高度的第一行导体，在第二行方向上延伸并设置在第二高度的第二行导体和沿列方向延伸的列导体并且设置成与第一行导体相邻并且与第二行导体相邻。阵列还包括覆盖列导体的至少一部分的电介质层，耦合在列导体上的电介质层和第二行导体之间的熔丝链。

2. 发明授权

US07888272B2 Methods for manufacturing memory and logic devices using the same process without the need for additional masks 有权
标题翻译：使用相同过程制造存储器和逻辑器件而不需要额外掩模的方法
公开(公告)号：US07888272B2
公开(公告)日：2011-02-15
申请号：US11609747
申请日：2006-12-12
申请人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming-Shang Chen , Shih Chin Lee
发明人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming-Shang Chen , Shih Chin Lee
IPC分类号： H01L21/318
CPC分类号： H01L21/3144 , H01L21/02238 , H01L21/02255 , H01L21/28238 , H01L21/31662 , H01L29/42332 , H01L29/518 , H01L29/66825 , H01L29/78 , H01L29/7883 , H01L29/7885
摘要： A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.
摘要翻译：半导体制造工艺允许使用常规CMOS工艺制造逻辑和存储器件，并且附加几个步骤。然而，额外的步骤不需要额外的掩模。因此，该过程可以降低在同一衬底上制造逻辑和存储器件的复杂性，时间和成本，特别是对于嵌入式应用。

3. 发明申请

US20080138998A1 METHODS FOR MANUFACTURING MEMORY AND LOGIC DEVICES USING THE SAME PROCESS WITHOUT THE NEED FOR ADDITIONAL MASKS 有权
标题翻译：使用相同工艺制造存储器和逻辑器件的方法，而不需要额外的掩码
公开(公告)号：US20080138998A1
公开(公告)日：2008-06-12
申请号：US11609747
申请日：2006-12-12
申请人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming-Shang Chen , Shih Chin Lee
发明人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming-Shang Chen , Shih Chin Lee
IPC分类号： H01L21/31
CPC分类号： H01L21/3144 , H01L21/02238 , H01L21/02255 , H01L21/28238 , H01L21/31662 , H01L29/42332 , H01L29/518 , H01L29/66825 , H01L29/78 , H01L29/7883 , H01L29/7885
摘要： A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.
摘要翻译：半导体制造工艺允许使用常规CMOS工艺制造逻辑和存储器件，并且附加几个步骤。然而，额外的步骤不需要额外的掩模。因此，该过程可以降低在同一衬底上制造逻辑和存储器件的复杂性，时间和成本，特别是对于嵌入式应用。

4. 发明申请

US20080026527A1 AN APPARATUS AND ASSOCIATED METHOD FOR MAKING A FLOATING GATE MEMORY DEVICE WITH INCREASED GATE COUPLING RATIO 有权
标题翻译：用于制造具有增加的门盖耦合比的浮动门存储器件的装置和相关方法
公开(公告)号：US20080026527A1
公开(公告)日：2008-01-31
申请号：US11460216
申请日：2006-07-26
申请人： Kuan Fu Chen , Yin Jen Chen , Meng Hsuan Weng , Tzung Ting Han , Ming Shang Chen , Chun Pei Wu
发明人： Kuan Fu Chen , Yin Jen Chen , Meng Hsuan Weng , Tzung Ting Han , Ming Shang Chen , Chun Pei Wu
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.
摘要翻译：一种用于制造浮动栅极存储器件的方法包括使用自对准工艺在不需要附加光刻步骤的部分栅极结构上形成第四多晶硅层。因此，可以实现增强的器件可靠性，因为可以以较低的栅极偏置电平保持更高的GCR。此外，可以减少流程复杂性，从而增加吞吐量并减少设备故障。

5. 发明授权

US08183106B2 Apparatus and associated method for making a floating gate memory device with buried diffusion dielectric structures and increased gate coupling ratio 有权
标题翻译：用于制造具有掩埋扩散电介质结构和增加的栅极耦合比的浮动栅极存储器件的装置和相关方法
公开(公告)号：US08183106B2
公开(公告)日：2012-05-22
申请号：US11460216
申请日：2006-07-26
申请人： Kuan Fu Chen , Yin Jen Chen , Meng Hsuan Weng , Tzung Ting Han , Ming Shang Chen , Chun Pei Wu
发明人： Kuan Fu Chen , Yin Jen Chen , Meng Hsuan Weng , Tzung Ting Han , Ming Shang Chen , Chun Pei Wu
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/8238
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.
摘要翻译：一种用于制造浮动栅极存储器件的方法包括使用自对准工艺在不需要附加光刻步骤的部分栅极结构上形成第四多晶硅层。因此，可以实现增强的器件可靠性，因为可以以较低的栅极偏置电平保持更高的GCR。此外，可以减少流程复杂性，从而增加吞吐量并减少设备故障。

6. 发明授权

US07515158B2 Modularly configurable memory system for LCD TV system 有权
标题翻译：用于液晶电视系统的模块化可配置存储系统
公开(公告)号：US07515158B2
公开(公告)日：2009-04-07
申请号：US11158872
申请日：2005-06-22
申请人： Peter Chang , Kuan Fu Chen
发明人： Peter Chang , Kuan Fu Chen
IPC分类号： G06T1/60
CPC分类号： H04N21/44004 , G09G5/001 , G09G5/39 , G09G2360/12 , H04N19/423 , H04N21/42692 , H04N21/443
摘要： A configurable memory system provides a high bandwidth, low latency, no wait state data path to a memory system functioning as a frame buffer for a digital video processing system. The configurable memory system has configurable channels that are programmable to control the access pattern of the memory controller. Once the configurable channels are programmed, the memory controller can generate the necessary address, timing, and control signals for selectively writing the data to and reading the data from the selected blocks of the array of memory devices continuously access the memory and move the data to the channel buffers. The channel buffer receives, retains, and transfers a defined segment of the data as defined by the segment pattern between the processing system and the array of memory devices, such that the processing system is able to transfer and receive the data continuously according to data requirements of the processing system.
摘要翻译：可配置的存储器系统提供高带宽，低等待时间，无等待状态数据路径到用作数字视频处理系统的帧缓冲器的存储器系统。可配置存储器系统具有可编程的可配置通道，以控制存储器控制器的访问模式。一旦可配置的通道被编程，存储器控制器可以产生必要的地址，定时和控制信号，用于选择性地将数据写入存储器件阵列的所选块并从其中读取数据，并持续访问存储器并将数据移动到通道缓冲区。信道缓冲器接收，保留和传送由处理系统和存储器件阵列之间的段模式定义的数据的定义段，使得处理系统能够根据数据要求连续地传送和接收数据的处理系统。

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