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1. 发明申请

US20120104352A1 MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：存储器件及其制造方法
公开(公告)号：US20120104352A1
公开(公告)日：2012-05-03
申请号：US13052426
申请日：2011-03-21
申请人： Kenji AOYAMA , Kazuhiko Yamamoto , Satoshi Ishikawa , Shigeto Oshino
发明人： Kenji AOYAMA , Kazuhiko Yamamoto , Satoshi Ishikawa , Shigeto Oshino
IPC分类号： H01L45/00 , H01L21/62 , B82Y10/00 , B82Y99/00 , B82Y40/00
CPC分类号： H01L45/1675 , B82Y10/00 , B82Y40/00 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/149
摘要： According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.
摘要翻译：根据一个实施例，存储器件包括纳米材料组装层，第一电极层和第二电极层。纳米材料组装层通过微导体之间的间隙由多个微导体的组件形成。第一电极层设置在纳米材料组装层上。第二电极层设置在第一电极层上。

2. 发明申请

US20120025159A1 NONVOLATILE MEMORY DEVICE 失效
标题翻译：非易失性存储器件
公开(公告)号：US20120025159A1
公开(公告)日：2012-02-02
申请号：US12973064
申请日：2010-12-20
申请人： Kenji AOYAMA , Kazuhiko Yamamoto
发明人： Kenji AOYAMA , Kazuhiko Yamamoto
IPC分类号： H01L45/00 , B82Y99/00
CPC分类号： B82Y30/00 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1226 , H01L45/149
摘要： According to one embodiment, a nonvolatile memory device includes a first conductive member and a second conductive member. The first conductive member extends in a first direction. The second conductive member extends in a second direction intersecting the first direction. A portion of the first conductive member connected to the second conductive member protrudes toward the second conductive member. A resistivity of the first conductive member in the first direction is lower than a resistivity of the first conductive member in a third direction of the protrusion of the first conductive member. A resistance value of the first conductive member in the third direction changes. A resistivity of the second conductive member in the second direction is lower than a resistivity of the second conductive member in the third direction. A resistance value of the second conductive member in the third direction changes.
摘要翻译：根据一个实施例，非易失性存储器件包括第一导电构件和第二导电构件。第一导电构件沿第一方向延伸。第二导电构件沿与第一方向相交的第二方向延伸。连接到第二导电构件的第一导电构件的一部分朝向第二导电构件突出。第一导电构件在第一方向上的电阻率低于第一导电构件在第一导电构件的突起的第三方向上的电阻率。第一导电构件在第三方向上的电阻值改变。第二导电构件在第二方向上的电阻率低于第二导电构件在第三方向上的电阻率。第二导电构件在第三方向上的电阻值改变。

3. 发明申请

US20120056145A1 NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20120056145A1
公开(公告)日：2012-03-08
申请号：US13018765
申请日：2011-02-01
申请人： Kenji AOYAMA , Kazuhiko Yamamoto , Satoshi Ishikawa , Shigeto Oshino
发明人： Kenji AOYAMA , Kazuhiko Yamamoto , Satoshi Ishikawa , Shigeto Oshino
IPC分类号： H01L45/00 , H01L21/02 , B82Y40/00 , B82Y30/00
CPC分类号： H01L45/16 , B82Y10/00 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/149 , H01L45/1608 , H01L45/1675
摘要： According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide.
摘要翻译：根据一个实施例，非易失性存储器件包括选择元件层和纳米材料聚集层。选择元件层包括硅。纳米材料聚集层层叠在选择元件层上。纳米材料聚集体层包括分散在微导电体之间的多个间隙中的多个微导电体和微粒。至少微细颗粒的表面由氧化硅以外的绝缘材料制成。

4. 发明申请

US20100176488A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100176488A1
公开(公告)日：2010-07-15
申请号：US12491296
申请日：2009-06-25
申请人： Kenji AOYAMA
发明人： Kenji AOYAMA
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L27/1021 , H01L27/24
摘要： A semiconductor memory device includes a word line interconnect layer having a plurality of word lines extending in a word line direction and a bit line interconnect layer having a plurality of bit lines extending in a bit line direction alternately stacked on a silicon substrate. A variable resistance film is disposed between the word line and the bit line. A first pin diode extending in the word line direction is provided between the word line and the variable resistance film, and a second pin diode extending in the bit line direction is provided between the bit line and the variable resistance film. A region of an upper surface of the pin diode other than an immediately underlying region of the variable resistance film is located lower than the immediately underlying region.
摘要翻译：半导体存储器件包括具有在字线方向上延伸的多个字线的字线互连层和具有交替层叠在硅衬底上的位线方向延伸的多个位线的位线互连层。可变电阻膜设置在字线和位线之间。在字线方向和可变电阻膜之间设置有沿字线方向延伸的第一PIN二极管，并且在位线和可变电阻膜之间设置沿位线方向延伸的第二pin二极管。引脚二极管的上表面的区域不同于可变电阻膜的紧邻下方区域的位置低于紧邻的下方区域。

5. 发明申请

US20130020629A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20130020629A1
公开(公告)日：2013-01-24
申请号：US13557295
申请日：2012-07-25
申请人： Kyoko ANDO , Satoshi NAGASHIMA , Kenji AOYAMA
发明人： Kyoko ANDO , Satoshi NAGASHIMA , Kenji AOYAMA
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/76229 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L29/66825 , H01L29/7883
摘要： According to one embodiment, a semiconductor memory device includes a plurality of word lines formed on a semiconductor substrate at predetermined intervals, selecting transistors arranged on at least one side of the plurality of word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and the selecting transistors, a first air gap located between each pair of adjacent ones of the word lines and covered by the interlayer insulating film, a second air gap located at a first side wall portion of a word line adjacent to the selecting transistors covered by the interlayer insulating film, the first side wall portion facing the selecting transistors, and a third air gap located at a second side wall portion of each of the selecting transistors and covered by the interlayer insulating film. The first, second, and third air gaps are filled with air.
摘要翻译：根据一个实施例，半导体存储器件包括以预定间隔形成在半导体衬底上的多个字线，选择排列在多个字线的至少一侧的晶体管，形成为覆盖所述多个字线的上表面的层间绝缘膜字线和选择晶体管，位于每对相邻字线之间并由层间绝缘膜覆盖的第一气隙，位于与选择晶体管相邻的字线的第一侧壁部分处的第二气隙被层间绝缘膜覆盖，面向选择晶体管的第一侧壁部分和位于每个选择晶体管的第二侧壁部分并被层间绝缘膜覆盖的第三气隙。第一，第二和第三气隙充满空气。

6. 发明申请

US20100237400A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100237400A1
公开(公告)日：2010-09-23
申请号：US12713652
申请日：2010-02-26
申请人： Kenji AOYAMA
发明人： Kenji AOYAMA
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11565 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device includes: a multilayer body with a plurality of insulating films and electrode films alternately stacked therein; a plurality of select gate electrodes provided on the multilayer body, extending in one direction orthogonal to a stacking direction of the multilayer body, and spaced from each other; semiconductor pillars penetrating through the multilayer body and the select gate electrodes; and a charge storage film provided between one of the electrode films and one of the semiconductor pillars, two neighboring ones of the semiconductor pillars penetrating through a common one of the select gate electrodes and penetrating through mutually different positions in a width direction of the select gate electrodes.
摘要翻译：非易失性半导体存储器件包括：具有多个绝缘膜和交替层叠的电极膜的多层体; 设置在所述多层体上的多个选择栅极，在与所述多层体的堆叠方向正交的一个方向上延伸并且彼此间隔开; 穿过多层体和选择栅电极的半导体柱; 以及电荷存储膜，其设置在所述电极膜之一和所述半导体柱之一之间，所述半导体柱中的两个相邻的所述半导体柱穿透所述选择栅电极中的公共的一个，并且穿过所述选择栅的宽度方向上的相互不同的位置电极。

7. 发明申请

US20090218614A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20090218614A1
公开(公告)日：2009-09-03
申请号：US12354271
申请日：2009-01-15
申请人： Kenji AOYAMA , Hisataka Meguro , Satoshi Nagashima
发明人： Kenji AOYAMA , Hisataka Meguro , Satoshi Nagashima
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28247 , H01L21/76229 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.
摘要翻译：半导体存储装置具有在半导体衬底上形成有预定间隔的多个字线，设置在多个字线的端部的选择晶体管，形成为覆盖字线的侧面的第一绝缘膜所述选择晶体管的侧面以及所述字线之间的所述半导体基板的表面，形成在所述第一绝缘膜上的高电容率膜，形成为覆盖所述字线的上表面的第二绝缘膜，以及选择晶体管，位于字线之间并被高电容率膜和第二绝缘膜包围的第一气隙部分和经由第一绝缘膜和高介电常数膜形成的第二气隙部分，与选择晶体管相邻的字线相对的选择晶体管的侧壁部分，第二气隙部分的上部被第二i 记录膜。

8. 发明申请

US20130234224A1 SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD FOR THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20130234224A1
公开(公告)日：2013-09-12
申请号：US13590586
申请日：2012-08-21
申请人： Kenji AOYAMA
发明人： Kenji AOYAMA
IPC分类号： H01L29/788 , H01L21/283
CPC分类号： H01L27/11524 , H01L29/40114
摘要： According to one embodiment, a semiconductor storage device comprises a memory cell transistor including a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film and a control gate which are sequentially formed on a substrate, and a select transistor including a fourth insulating film, a first electrode layer, a fifth insulating film, a second electrode layer, a sixth insulating film and a third electrode layer which are sequentially formed on the substrate. Openings are provided in at least parts of the fifth insulating film and the sixth insulating film. The first electrode layer, the second electrode layer and the third electrode layer are electrically connected via the openings.
摘要翻译：根据一个实施例，半导体存储装置包括存储单元晶体管，其包括依次形成在衬底上的第一绝缘膜，第一浮栅，第二绝缘膜，第二浮栅，第三绝缘膜和控制栅极以及依次形成在基板上的包括第四绝缘膜，第一电极层，第五绝缘膜，第二电极层，第六绝缘膜和第三电极层的选择晶体管。开口设置在第五绝缘膜和第六绝缘膜的至少一部分中。第一电极层，第二电极层和第三电极层经由开口电连接。

9. 发明申请

US20090212352A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20090212352A1
公开(公告)日：2009-08-27
申请号：US12391953
申请日：2009-02-24
申请人： Kenji AOYAMA , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
发明人： Kenji AOYAMA , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
IPC分类号： H01L29/792 , H01L21/28 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/764 , H01L29/66825
摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.
摘要翻译：半导体存储器件具有半导体衬底，在半导体衬底上以预定间隔形成的多个字线，每个字线具有栅极绝缘膜，电荷存储层，第一绝缘膜和控制栅电极，它们被堆叠并且包括位于栅极绝缘膜的高度之上的金属氧化物层，覆盖字线的一侧的第二绝缘膜和字线之间的半导体衬底的表面，并且具有15nm的膜厚度或并且形成在彼此相邻的字线之间的第三绝缘膜，使得低于金属氧化物层的电平的区域具有空腔。

10. 发明申请

US20080185630A1 STACKED GATE NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：嵌入式门非易失性半导体存储器及其制造方法
公开(公告)号：US20080185630A1
公开(公告)日：2008-08-07
申请号：US11927799
申请日：2007-10-30
申请人： Kenji AOYAMA , Satoshi Nagashima
发明人： Kenji AOYAMA , Satoshi Nagashima
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A stacked gate nonvolatile semiconductor memory includes at least a memory cell transistor and a selective gate transistor which are formed on a semiconductor substrate. The memory cell transistor includes a floating gate made of a semiconductor material below an interlayer insulating layer and a control gate made of a silicide above the interlayer insulating layer. The selective gate transistor includes a semiconductor layer made of the semiconductor material, a silicide layer made of the silicide and a conductive layer made of a conductive material not subject to silicide process which is formed through the interlayer insulating film so as to electrically connect the semiconductor layer and the silicide layer.
摘要翻译：层叠栅极非易失性半导体存储器至少包括形成在半导体衬底上的存储单元晶体管和选择栅极晶体管。存储单元晶体管包括由层间绝缘层下方的半导体材料制成的浮置栅极和由层间绝缘层上方的硅化物制成的控制栅极。选择栅晶体管包括由半导体材料制成的半导体层，由硅化物制成的硅化物层和由不经过硅化处理的导电材料制成的导电层，该导电层通过层间绝缘膜形成，以将半导体层和硅化物层。

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