专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120112208A1 STRESSED TRANSISTOR WITH IMPROVED METASTABILITY 有权
标题翻译：具有改进的均匀性的应力晶体管
公开(公告)号：US20120112208A1
公开(公告)日：2012-05-10
申请号：US12942289
申请日：2010-11-09
申请人： THOMAS N. ADAM , Stephen W. Bedell , Abhishek Dube , Eric C.T. Harley , Judson R. Holt , Alexander Reznicek , Devendra K. Sadana , Dominic J. Schepis , Matthew W. Stoker , Keith H. Tabakman
发明人： THOMAS N. ADAM , Stephen W. Bedell , Abhishek Dube , Eric C.T. Harley , Judson R. Holt , Alexander Reznicek , Devendra K. Sadana , Dominic J. Schepis , Matthew W. Stoker , Keith H. Tabakman
IPC分类号： H01L29/772 , H01L29/24 , H01L21/336
CPC分类号： H01L29/78 , H01L21/28525 , H01L21/76805 , H01L21/76877 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.
摘要翻译：在至少一个预制的场效应晶体管的覆盖区上形成嵌入的应变外延半导体材料，即嵌入的应力元件，该至少一个预制的场效应晶体管至少包括图案化的栅叠层，源极区和漏极区。结果，保留嵌入的应变外延半导体材料的亚稳态，并且避免基于植入和退火的松弛机制，因为在形成嵌入的应变外延半导体材料之前执行注入和退火。

2. 发明申请

US20100090288A1 METHOD OF FORMING SOURCE AND DRAIN OF A FIELD-EFFECT-TRANSISTOR AND STRUCTURE THEREOF 有权
标题翻译：形成源极和场效应晶体管的方法及其结构
公开(公告)号：US20100090288A1
公开(公告)日：2010-04-15
申请号：US12248970
申请日：2008-10-10
申请人： Judson R. Holt , Abhishek Dube , Eric C.T. Harley , Shwu-Jen Jeng , Jeremy J. Kempisty , Hasan Munir Nayfeh , Keith Howard Tabakman
发明人： Judson R. Holt , Abhishek Dube , Eric C.T. Harley , Shwu-Jen Jeng , Jeremy J. Kempisty , Hasan Munir Nayfeh , Keith Howard Tabakman
IPC分类号： H01L29/00 , H01L21/8238
CPC分类号： H01L29/7848 , H01L27/11 , H01L27/1104 , H01L29/1083 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process.
摘要翻译：公开了涉及使用eSiGe的半导体制造方法。 eSiGe方法对于将期望的应力施加到场效应晶体管的沟道区域是有用的，但是也可能在半导体制造工艺中引入复杂性。本发明的实施方案公开了两步制备方法，其中使用低氢气流速施加第一层eSiGe，并且使用更高的氢气流速施加第二eSiGe层。这种方法提供了一种平衡形态权衡的方法，并在使用eSiGe时填补一致性。本发明的实施例促进了钉扎形态，其降低了对外延厚度的器件灵敏度，同时还在各种器件宽度之间提供更一致的填充体积，从而提供更一致的eSiGe半导体制造工艺。

3. 发明申请

US20100112762A1 METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURES 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US20100112762A1
公开(公告)日：2010-05-06
申请号：US12684551
申请日：2010-01-08
申请人： Thomas N. Adam , Ashima B. Chakravarti , Eric C.T. Harley , Judson R. Holt
发明人： Thomas N. Adam , Ashima B. Chakravarti , Eric C.T. Harley , Judson R. Holt
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L29/66545 , H01L21/0237 , H01L21/02422 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/0262 , H01L21/02636 , H01L21/0332 , H01L21/0337 , H01L21/32139 , H01L21/76224 , H01L29/165 , H01L29/41783 , H01L29/66553
摘要： Methods of fabricating a semiconductor structure with a non- epitaxial thin film disposed on a surface of a substrate of the semiconductor structure are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process. Such resultant/intermediate structures may be used, for example, but are not limited to: source-drain fabrication; hardmask strengthening; spacer widening; high-aspect-ratio (HAR) vias filling; micro-electro-mechanical-systems (MEMS) fabrication; FEOL resistor fabrication; lining of shallow trench isolations (STI) and deep trenches; critical dimension (CD) tailoring and claddings.
摘要翻译：公开了制造具有设置在半导体结构的衬底的表面上的非外延薄膜的半导体结构的方法。该方法提供非晶和/或多晶材料的选择性非外延生长（SNEG）或沉积以在其表面上形成薄膜。表面可以是非结晶介电材料或结晶材料。非结晶电介质上的SNEG还通过仔细选择前体载体 - 蚀刻剂比例，进一步提供非晶/多晶材料对氧化物上的氮化物的选择性生长。非外延薄膜形成可并入到任何前端（FEOL）制造工艺中的所得和/或中间半导体结构。这样的合成/中间结构可以用于例如但不限于：源极 - 漏极制造; 硬掩模强化; 间隔加宽; 高纵横比（HAR）通孔填充; 微电子机械系统（MEMS）制造; FEOL电阻制造; 浅沟槽隔离（STI）和深沟槽衬砌; 临界尺寸（CD）裁剪和包层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式