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1. 发明授权

US08331190B2 Semiconductor memory device and operation method thereof 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08331190B2
公开(公告)日：2012-12-11
申请号：US13172191
申请日：2011-06-29
申请人： Sun-Hyuck Yon , Kee-Teok Park
发明人： Sun-Hyuck Yon , Kee-Teok Park
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C5/144 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.
摘要翻译：半导体存储器件包括：时钟同步单元，用于通过第一电源电压端子接收第一电源电压;以及附加电源电压提供单元，用于在离开电源之后在预定时间段内向第一电源电压额外提供第二电源电压下模式。

2. 发明申请

US20110210769A1 INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路
公开(公告)号：US20110210769A1
公开(公告)日：2011-09-01
申请号：US12982717
申请日：2010-12-30
申请人： Kee-Teok PARK
发明人： Kee-Teok PARK
IPC分类号： H03L7/00
CPC分类号： G11C7/109 , G11C7/20 , G11C11/4072
摘要： An integrated circuit includes a pad, an input buffer unit, and a supplementary driving unit. The pad is configured to receive a reset signal from an external device. The input buffer unit is configured to buffer a reset signal applied to the pad. The supplementary driving unit is configured to receive an output signal from the input buffer unit and supplementarily drive an input terminal of the input buffer unit to a deactivation level of the reset signal.
摘要翻译：集成电路包括焊盘，输入缓冲单元和辅助驱动单元。该焊盘被配置为从外部设备接收复位信号。输入缓冲器单元被配置为缓冲施加到焊盘的复位信号。辅助驱动单元被配置为从输入缓冲器单元接收输出信号，并将输入缓冲器单元的输入端辅助驱动到复位信号的去激活电平。

3. 发明申请

US20100329040A1 DATA ALIGNMENT CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：数据对准电路和半导体存储器件的方法
公开(公告)号：US20100329040A1
公开(公告)日：2010-12-30
申请号：US12649066
申请日：2009-12-29
申请人： Chun Seok JEONG , Kee Teok PARK , Chang Sik YOO , Jang Woo LEE , Hong Jung KIM
发明人： Chun Seok JEONG , Kee Teok PARK , Chang Sik YOO , Jang Woo LEE , Hong Jung KIM
IPC分类号： G11C7/10 , G11C7/00 , G11C8/18
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/222
摘要： A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of data phase control blocks configured to control phases of input data in response to data delay codes and generate delayed data; a plurality of data alignment blocks configured to latch the delayed data in response to the delayed strobe clock signal and generate latched data and aligned data; and a delay code generation block configured to perform an operation of determining phases of the latched data and generate the strobe delay code and the data delay codes.
摘要翻译：半导体存储装置的数据对准电路包括：数据选通时钟相位控制块，被配置为响应于选通延迟码来控制数据选通时钟信号的相位，并产生延迟的选通时钟信号; 多个数据相位控制块，被配置为响应于数据延迟码来控制输入数据的相位并产生延迟的数据; 多个数据对准块被配置为响应延迟的选通时钟信号来锁存延迟的数据，并产生锁存的数据和对准的数据; 以及延迟码生成块，被配置为执行确定所述锁存数据的相位的操作，并生成所述选通延迟码和所述数据延迟码。

4. 发明申请

US20090168584A1 SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20090168584A1
公开(公告)日：2009-07-02
申请号：US12165065
申请日：2008-06-30
申请人： Sun-Hyuck YON , Kee-Teok Park
发明人： Sun-Hyuck YON , Kee-Teok Park
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C5/144 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.
摘要翻译：半导体存储器件包括：时钟同步单元，用于通过第一电源电压端子接收第一电源电压;以及附加电源电压提供单元，用于在离开电源之后在预定时间段内向第一电源电压额外提供第二电源电压下模式。

5. 发明申请

US20080212383A1 Circuit and method for parallel test of memory device 失效
标题翻译：存储器件并行测试电路及方法
公开(公告)号：US20080212383A1
公开(公告)日：2008-09-04
申请号：US12000123
申请日：2007-12-10
申请人： Young-Jun Ku , Kee-Teok Park
发明人： Young-Jun Ku , Kee-Teok Park
IPC分类号： G11C29/00
CPC分类号： G11C29/40 , G11C2029/2602
摘要： A test circuit in a memory device includes a first compression unit configured to compress data of a plurality of cells to transmit first compressed data to a plurality of input/output lines, and a second compression unit configured to compress the first compressed data on the plurality of input/output line to output second compressed data to at least one output pin, wherein the second compression unit operates in a low compressing mode and a high compressing mode in response to a data compression selecting signal.
摘要翻译：存储器件中的测试电路包括：第一压缩单元，被配置为压缩多个单元的数据以将第一压缩数据发送到多个输入/输出线;以及第二压缩单元，被配置为压缩多个单元上的第一压缩数据输出/输出线以将第二压缩数据输出到至少一个输出引脚，其中响应于数据压缩选择信号，第二压缩单元以低压缩模式和高压缩模式操作。

6. 发明申请

US20080082291A1 On die thermal sensor 有权
标题翻译：模具热传感器
公开(公告)号：US20080082291A1
公开(公告)日：2008-04-03
申请号：US11647351
申请日：2006-12-29
申请人： Chun-Seok Jeong , Kee-Teok Park
发明人： Chun-Seok Jeong , Kee-Teok Park
IPC分类号： G06F19/00
CPC分类号： G01K7/015
摘要： An on die thermal sensor (ODTS) for use in a semiconductor memory device includes: a temperature information code generation unit for sensing an internal temperature of the semiconductor memory device in response to first and second enable signals and for generating a temperature information code which includes the sensed temperature information; and a flag signal logic determination unit for generating a plurality of first flag signals having temperature information and determining whether the plurality of first flag signals have a predetermined logic level or a variable logic level in response to the first and second enable signals.
摘要翻译：一种用于半导体存储器件的裸片热传感器（ODTS）包括：温度信息代码生成单元，用于响应于第一和第二使能信号感测半导体存储器件的内部温度，并用于产生温度信息代码，其包括感测温度信息; 以及标志信号逻辑确定单元，用于产生具有温度信息的多个第一标志信号，并且响应于第一和第二使能信号确定多个第一标志信号是否具有预定逻辑电平或可变逻辑电平。

7. 发明授权

US07193906B2 Voltage regulating circuit and method of regulating voltage 有权
标题翻译：调压电路及调压方法
公开(公告)号：US07193906B2
公开(公告)日：2007-03-20
申请号：US11008672
申请日：2004-12-10
申请人： Ji Eun Jang , Kee Teok Park
发明人： Ji Eun Jang , Kee Teok Park
IPC分类号： G11C5/14
CPC分类号： G11C29/021 , G11C7/12 , G11C11/401 , G11C11/4074 , G11C11/4094 , G11C29/028 , G11C2029/5004
摘要： Provided is concerned with a voltage regulation circuit and method of regulating the voltage, including a reference voltage generator for generating a reference voltage by dividing a core voltage of a semiconductor memory device, a controller for controlling the reference voltage generator to adjust the reference voltage without handling the core voltage in response to a test signal of a test mode, and a voltage generator for generating a bit-line precharging voltage and/or a cell plate voltage in accordance with the reference voltage.
摘要翻译：关于电压调节电路和调节电压的方法，包括用于通过划分半导体存储器件的芯电压来产生参考电压的参考电压发生器，用于控制参考电压发生器的控制器，以在没有响应于测试模式的测试信号处理核心电压;以及电压发生器，用于根据参考电压产生位线预充电电压和/或单元板电压。

8. 发明授权

US08526251B2 Semiconductor apparatus, method for delaying signal thereof, stacked semiconductor memory apparatus, and method for generating signal thereof 有权
公开(公告)号：US08526251B2
公开(公告)日：2013-09-03
申请号：US12970882
申请日：2010-12-16
申请人： Heat Bit Park , Kee Teok Park
发明人： Heat Bit Park , Kee Teok Park
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C5/063 , G11C7/222
摘要： The semiconductor apparatus includes a reference delay value check unit configured to receive a source signal and delay the source signal to generate a reference delay signal; a process delay value check unit configured to receive the source signal and delay the source signal to generate a process delay signal; and a signal generation unit configured to receive the reference delay signal and the process delay signal, receive an input signal, and variably delay the input signal based on the reference delay signal and the process delay signal to generate an output signal.

9. 发明申请

US20120105124A1 SEMICONDUCTOR APPARATUS, METHOD FOR DELAYING SIGNAL THEREOF, STACKED SEMICONDUCTOR MEMORY APPARATUS, AND METHOD FOR GENERATING SIGNAL THEREOF 有权
标题翻译：半导体装置，其延迟信号的方法，堆叠式半导体存储装置及其信号生成方法
公开(公告)号：US20120105124A1
公开(公告)日：2012-05-03
申请号：US12970882
申请日：2010-12-16
申请人： Heat Bit PARK , Kee Teok Park
发明人： Heat Bit PARK , Kee Teok Park
IPC分类号： H03H11/26
CPC分类号： G11C7/00 , G11C5/063 , G11C7/222
摘要： The semiconductor apparatus includes a reference delay value check unit configured to receive a source signal and delay the source signal to generate a reference delay signal; a process delay value check unit configured to receive the source signal and delay the source signal to generate a process delay signal; and a signal generation unit configured to receive the reference delay signal and the process delay signal, receive an input signal, and variably delay the input signal based on the reference delay signal and the process delay signal to generate an output signal.
摘要翻译：该半导体装置包括基准延迟值检查单元，被配置为接收源信号并延迟源信号以产生参考延迟信号; 处理延迟值检查单元，被配置为接收源信号并延迟源信号以产生处理延迟信号; 以及信号生成单元，被配置为接收参考延迟信号和处理延迟信号，接收输入信号，并且基于参考延迟信号和处理延迟信号可变地延迟输入信号以产生输出信号。

10. 发明授权

US08140293B2 On die thermal sensor 有权
标题翻译：模具热传感器
公开(公告)号：US08140293B2
公开(公告)日：2012-03-20
申请号：US11819810
申请日：2007-06-29
申请人： Chun-Seok Jeong , Kee-Teok Park
发明人： Chun-Seok Jeong , Kee-Teok Park
IPC分类号： G01K7/00 , G01R31/00
CPC分类号： G01K7/425 , G11C7/04 , G11C11/406 , G11C11/40626
摘要： An on die thermal sensor (ODTS) for use in a semiconductor device includes a temperature information output unit for measuring an internal temperature of the semiconductor device to generate a temperature information code having temperature information, and updating the temperature information code according to a refresh period.
摘要翻译：用于半导体器件的裸片热传感器（ODTS）包括温度信息输出单元，用于测量半导体器件的内部温度以产生具有温度信息的温度信息代码，并根据刷新周期更新温度信息代码。

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