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1. 发明授权

US08922304B2 Laminated electronic devices with conical vias 有权
标题翻译：具有锥形通孔的层压电子设备
公开(公告)号：US08922304B2
公开(公告)日：2014-12-30
申请号：US13280734
申请日：2011-10-25
申请人： Kazunari Kimura , Junichi Nakamura , Takeshi Kijima , Isao Abe , Takahiro Suzuki , Toshiaki Araki
发明人： Kazunari Kimura , Junichi Nakamura , Takeshi Kijima , Isao Abe , Takahiro Suzuki , Toshiaki Araki
IPC分类号： H01P1/203 , H05K3/40 , H05K3/46
CPC分类号： H05K3/4061 , H01P1/20345 , H05K3/4629 , Y10T29/49165
摘要： A laminated electronic device comprises two or more wiring layers including a first wiring layer and a second wiring layer, an insulating layer interposed between the first wiring layer and second wiring layer, and a through conductor extending through the insulating layer for electrically connecting a first conductor disposed on the first wiring layer to a second conductor disposed on the second wiring layer. The through conductor includes divergent sections at both ends, which have a diameter gradually increased toward the first conductor or second conductor.
摘要翻译：层叠电子器件包括两个或更多个布线层，包括第一布线层和第二布线层，插入在第一布线层和第二布线层之间的绝缘层，以及穿过绝缘层的贯通导体，用于将第一布线布置在第一布线层上的布置在第二布线层上的第二导体。贯通导体包括两端的发散部分，其具有朝向第一导体或第二导体逐渐增加的直径。

2. 发明申请

US20100229139A1 SYSTEM AND METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：用于设计半导体集成电路的系统和方法
公开(公告)号：US20100229139A1
公开(公告)日：2010-09-09
申请号：US12702129
申请日：2010-02-08
申请人： Miyako KITAOKA , Kazunari KIMURA
发明人： Miyako KITAOKA , Kazunari KIMURA
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： An extraction unit extracts a metal pattern constituting a semiconductor integrated circuit from layout data. A setting unit sets up a region including the metal pattern extracted by the extraction unit. An evaluation unit calculates the metal coverage rate of the region and to evaluate whether the metal coverage rate is equal to or more than a predetermined value. An insertion unit inserts a dummy metal pattern into the region when the metal coverage rate is evaluated as a value smaller than the predetermined value by the evaluation unit.
摘要翻译：提取单元从布局数据中提取构成半导体集成电路的金属图案。设置单元设置包括由提取单元提取的金属图案的区域。评估单元计算该区域的金属覆盖率并评估金属覆盖率是否等于或大于预定值。当通过评估单元将金属覆盖率评估为小于预定值的值时，插入单元将虚设金属图案插入到该区域中。

3. 发明授权

US06203325B1 Dental magnetic attachment and its fixing method including spacer 失效
标题翻译：牙科磁性附件及其固定方法包括间隔
公开(公告)号：US06203325B1
公开(公告)日：2001-03-20
申请号：US09381977
申请日：1999-10-05
申请人： Yoshinobu Honkura , Kazuo Arai , Kazunari Kimura
发明人： Yoshinobu Honkura , Kazuo Arai , Kazunari Kimura
IPC分类号： A61C1312
CPC分类号： A61C13/235
摘要： A dental magnetic attachment having good cushioning properties against a compressing pressure which makes a denture sink appropriately on biting. The dental magnetic attachment embedded in the denture base for holding the denture in the oral cavity by a magnetic attractive force working with the magnetic assembly and a soft magnetic keeper embedded in the top of the root surface includes a magnetic assembly and a cap covering the top of the magnetic assembly. The magnetic assembly has a hollow in the center of its top. The cap with a button is placed on the magnetic assembly, inserting the button into the hollow to contact to its bottom. On biting, the button is compressed, to be deformed with a shorter thickness and at this time a sleeve formed as a body around the core slides down along the side of the magnetic assembly to reduce the thickness of the dental magnetic attachment. This sliding makes the denture sink uniformly and appropriately. The dental magnetic attachment has good cushioning properties and offers a good feeling to a patient when biting with the denture.
摘要翻译：牙科磁性附件具有抵抗压缩压力的良好缓冲性能，这使得义齿在咬合时适当地下沉。嵌入在义齿基座中的牙科磁性附件通过与磁性组件一起工作的磁性吸引力和嵌入根表面顶部的软磁保持器将义齿保持在口腔中，包括磁性组件和覆盖顶部的帽的磁性组件。磁性组件在其顶部的中心具有中空部分。带有按钮的盖子放置在磁性组件上，将按钮插入空腔中以接触其底部。在咬住时，按钮被压缩，以更短的厚度变形，此时，作为主体围绕芯部形成的套筒沿着磁性组件的侧面向下滑动以减小牙齿磁性附件的厚度。这种滑动使得义齿沉没均匀和适当。牙齿磁性附件具有良好的缓冲性能，并且在与义齿咬合时对患者提供良好的感觉。

4. 发明授权

US08864925B2 Method for producing laminated electronic component, and laminated electronic component 有权
标题翻译：层叠电子部件的制造方法以及层叠电子部件
公开(公告)号：US08864925B2
公开(公告)日：2014-10-21
申请号：US13811167
申请日：2011-07-21
申请人： Kazunari Kimura , Misaki Tabata , Shigemitsu Tomaki , Akira Nakamura , Isao Abe , Noriyuki Saito
发明人： Kazunari Kimura , Misaki Tabata , Shigemitsu Tomaki , Akira Nakamura , Isao Abe , Noriyuki Saito
IPC分类号： C03B29/00 , H01G4/40 , H01G4/005 , B32B18/00 , B32B5/00 , B32B38/00 , H01G4/30 , H01G4/12 , B29C65/00 , H03H1/00 , H03H7/01
CPC分类号： B32B38/0004 , B32B5/00 , B32B18/00 , B32B38/0036 , C04B2237/34 , C04B2237/343 , C04B2237/346 , C04B2237/68 , C04B2237/704 , C04B2237/76 , C04B2237/80 , H01G4/005 , H01G4/12 , H01G4/30 , H01G4/40 , H03H7/0115 , H03H2001/0085 , Y10T156/1089 , Y10T428/24058
摘要： A method of manufacturing a laminated electronic part includes fabricating first and second laminated sheets by laminating an insulating function layer made of an unsintered ceramic material and a conductor layer, having a plurality of conductors two-dimensionally arranged in a vertical direction and in a horizontal direction to make up part of circuit components; cutting the first and second laminated sheets into sticks to create a plurality of first and second laminate sticks; fabricating a third laminated sheet by rotating the second laminate sticks by 90°, arranging the second laminate sticks to be each sandwiched between the first laminate sticks, and thermocompression bonding them for integration; singulating the third laminated sheet into chips and creating sintered bodies by sintering the unsintered chips to integrate the first laminate with the second laminate.
摘要翻译：层叠电子部件的制造方法包括：通过层叠由烧结陶瓷材料制成的绝缘功能层和导体层来制造第一层压片和第二层叠片，所述导体层具有沿垂直方向和水平方向二维排列的多个导体组成电路元件的一部分; 将第一和第二层压片切割成棒以产生多个第一和第二层压棒; 通过将第二层压棒旋转90°来制造第三层压片，将第二层压棒布置在每个夹在第一层压棒之间，并将它们热压粘合用于一体化; 将第三层压片材切成芯片并通过烧结未烧结的芯片来制造烧结体，以将第一层压体与第二层压体集成。

5. 发明申请

US20130074027A1 DESIGNING DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGNING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：用于半导体集成电路的设计器件和半导体集成电路的设计方法
公开(公告)号：US20130074027A1
公开(公告)日：2013-03-21
申请号：US13422236
申请日：2012-03-16
申请人： Kazunari KIMURA
发明人： Kazunari KIMURA
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A designing device for a semiconductor integrated circuit of an embodiment includes a low-order hierarchy wiring design portion configured to design a first wiring; and a high-order hierarchy wiring design portion configured to design a second wiring. The low-order hierarchy wiring design portion divides the first functional block into a plurality of small regions, calculates a number of wiring layers required for wiring in the functional block for each of the plurality of small regions and sets the number as the number of low-order hierarchy wiring layers, sets wiring layers in the number of the low-order hierarchy wiring layers from the wiring layer located on the lowermost part as a low-order hierarchy wiring region for each of the plurality of small regions, and places the first wiring in the low-order hierarchy wiring region.
摘要翻译：实施例的半导体集成电路的设计装置包括被配置为设计第一布线的低阶层布线设计部分; 以及配置为设计第二布线的高阶层布线设计部分。低级布线设计部将第一功能块分割为多个小区域，计算多个小区域中的每一个的功能块中布线所需的布线层数，并将该数量设定为低将位于最下部的布线层的低层布线层的数量的布线层设置为多个小区域中的每一个的低层布线区域的布线层，并且将第一层布线层布线在低层布线区域。

6. 发明申请

US20090020850A1 SEMICONDUCTOR DESIGN APPARATUS, SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR DESIGN METHOD 审中-公开
标题翻译：半导体设计装置，半导体电路和半导体设计方法
公开(公告)号：US20090020850A1
公开(公告)日：2009-01-22
申请号：US12174921
申请日：2008-07-17
申请人： Hiroshige Orita , Kazunari Kimura , Toshiaki Mori
发明人： Hiroshige Orita , Kazunari Kimura , Toshiaki Mori
IPC分类号： H01L23/64 , G06F17/50
CPC分类号： H01L23/5223 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： According to an aspect of the present invention, there is provided a semiconductor design apparatus including: a determination section that determines a connection position of a capacitor to suppress a noise on a layout data in which a layout of circuit cells are completed; a calculation section that calculates a capacitance value required to suppress the noise; a generation section that generates the capacitor satisfying the capacitance value; and a wiring section that wires the capacitor to a power wiring and a ground wiring at the connection position.
摘要翻译：根据本发明的一个方面，提供了一种半导体设计装置，包括：确定部，确定电容器的连接位置，以抑制电路单元布局完成的布局数据上的噪声; 计算部，其计算抑制噪声所需的电容值; 产生满足电容值的电容器的发生部分; 以及将电容器连接到连接位置处的电力布线和接地布线的布线部。

7. 发明申请

US20130266758A2 METHOD FOR PRODUCING LAMINATED ELECTRONIC COMPONENT, AND LAMINATED ELECTRONIC COMPONENT 有权
标题翻译：生产层压电子元件的方法和层压电子元件
公开(公告)号：US20130266758A2
公开(公告)日：2013-10-10
申请号：US13811167
申请日：2011-07-21
申请人： Kazunari Kimura , Misaki Tabata , Shigemitsu Tomaki , Akira Nakamura , Isao Abe , Noriyuki Saito
发明人： Kazunari Kimura , Misaki Tabata , Shigemitsu Tomaki , Akira Nakamura , Isao Abe , Noriyuki Saito
IPC分类号： B32B38/00 , B32B18/00 , B32B5/00
CPC分类号： B32B38/0004 , B32B5/00 , B32B18/00 , B32B38/0036 , C04B2237/34 , C04B2237/343 , C04B2237/346 , C04B2237/68 , C04B2237/704 , C04B2237/76 , C04B2237/80 , H01G4/005 , H01G4/12 , H01G4/30 , H01G4/40 , H03H7/0115 , H03H2001/0085 , Y10T156/1089 , Y10T428/24058
摘要： A method of manufacturing a laminated electronic part includes fabricating first and second laminated sheets by laminating an insulating function layer made of an unsintered ceramic material and a conductor layer, having a plurality of conductors two-dimensionally arranged in a vertical direction and in a horizontal direction to make up part of circuit components; cutting the first and second laminated sheets into sticks to create a plurality of first and second laminate sticks; fabricating a third laminated sheet by rotating the second laminate sticks by 90°, arranging the second laminate sticks to be each sandwiched between the first laminate sticks, and thermocompression bonding them for integration; singulating the third laminated sheet into chips and creating sintered bodies by sintering the unsintered chips to integrate the first laminate with the second laminate.
摘要翻译：层叠电子部件的制造方法包括：通过层叠由烧结陶瓷材料制成的绝缘功能层和导体层来制造第一层压片和第二层叠片，所述导体层具有沿垂直方向和水平方向二维排列的多个导体组成电路元件的一部分; 将第一和第二层压片切割成棒以产生多个第一和第二层压棒; 通过将第二层压棒旋转90°来制造第三层压片，将第二层压棒布置在每个夹在第一层压棒之间，并将它们热压粘合用于一体化; 将第三层压片材切成芯片并通过烧结未烧结的芯片来制造烧结体，以将第一层压体与第二层压体集成。

8. 发明申请

US20070049178A1 Method and apparatus for fluid polishing 失效
标题翻译：流体抛光方法和装置
公开(公告)号：US20070049178A1
公开(公告)日：2007-03-01
申请号：US11509749
申请日：2006-08-24
申请人： Yasuhito Ooka , Shinichi Kato , Kazunari Kimura , Shigeya Kato
发明人： Yasuhito Ooka , Shinichi Kato , Kazunari Kimura , Shigeya Kato
IPC分类号： B24B1/00
CPC分类号： B24B31/116 , B24B1/00
摘要： In a fluid polishing method for processing a fine aperture by slurry 7, the slurry is supplied from a cylinder 2a in a slurry flow rate target process until the flow rate increases to a target value of a slurry feed flow rate. When the flow rate reaches the target flow-rate, the cylinder is stopped and switched to another cylinder 2b and the operation fluid flow rate of the fine aperture is thereafter measured. In a metering process, to be executed next, a necessary processing time is calculated on the basis of the operation fluid flow rate and polishing is carried out for a necessary processing time by another cylinder 2b. Another cylinder is then stopped and switched and the operation fluid flow rate is measured. In this way, the metering process is repeated until the operation fluid flow rate reaches a predetermined value. In each process, the supply of the slurry is not interrupted.
摘要翻译：在通过浆料7处理细孔的流体研磨方法中，浆料从浆料流量目标工艺中的气缸2a供给，直到流量增加到浆料进料流量的目标值。当流量达到目标流量时，停止气缸并切换到另一气缸2b，然后测量微孔的操作流体流量。在接下来执行的计量过程中，基于操作流体流量计算必要的处理时间，并且通过另一个气缸bb对所需的处理时间进行抛光。然后停止并切换另一个气缸并测量操作流体流量。以这种方式，重复计量过程，直到操作流体流量达到预定值。在每个过程中，浆料的供应不会中断。

9. 发明申请

US20130115411A1 METHOD FOR PRODUCING LAMINATED ELECTRONIC COMPONENT, AND LAMINATED ELECTRONIC COMPONENT 有权
公开(公告)号：US20130115411A1
公开(公告)日：2013-05-09
申请号：US13811167
申请日：2011-07-21
申请人： Kazunari Kimura , Misaki Tabata , Shigemitsu Tomaki , Akira Nakamura , Isao Abe , Noriyuki Saito
发明人： Kazunari Kimura , Misaki Tabata , Shigemitsu Tomaki , Akira Nakamura , Isao Abe , Noriyuki Saito
IPC分类号： B32B38/00 , B32B18/00 , B32B5/00
CPC分类号： B32B38/0004 , B32B5/00 , B32B18/00 , B32B38/0036 , C04B2237/34 , C04B2237/343 , C04B2237/346 , C04B2237/68 , C04B2237/704 , C04B2237/76 , C04B2237/80 , H01G4/005 , H01G4/12 , H01G4/30 , H01G4/40 , H03H7/0115 , H03H2001/0085 , Y10T156/1089 , Y10T428/24058
摘要： A method of manufacturing a laminated electronic part includes fabricating first and second laminated sheets by laminating an insulating function layer made of an unsintered ceramic material and a conductor layer, having a plurality of conductors two-dimensionally arranged in a vertical direction and in a horizontal direction to make up part of circuit components; cutting the first and second laminated sheets into sticks to create a plurality of first and second laminate sticks; fabricating a third laminated sheet by rotating the second laminate sticks by 90°, arranging the second laminate sticks to be each sandwiched between the first laminate sticks, and thermocompression bonding them for integration; singulating the third laminated sheet into chips and creating sintered bodies by sintering the unsintered chips to integrate the first laminate with the second laminate.

10. 发明申请

US20120313743A1 LAMINATED ELECTRONIC COMPONENT EQUIPPED WITH INDUCTOR 审中-公开
标题翻译：带电感器的层压电子元件
公开(公告)号：US20120313743A1
公开(公告)日：2012-12-13
申请号：US13580021
申请日：2011-09-07
申请人： Kazunari Kimura , Shigemitsu Tomaki , Misaki Tabata , Isao Abe
发明人： Kazunari Kimura , Shigemitsu Tomaki , Misaki Tabata , Isao Abe
IPC分类号： H01F5/00
CPC分类号： H01F17/0013 , H01F2017/004
摘要： A laminated electronic part comprises a first laminate, and a second laminate including a front wiring layer and bonded to the first laminate. Wiring layers of the first laminate and second laminate are orthogonal to each other. The first laminate has a first inductor conductor disposed on a first wiring layer, and a second inductor conductor disposed on a second wiring layer. The second laminate has a connection conductor for electrically connecting an end of the first inductor conductor with an end of the second inductor conductor on a surface thereof to which the first laminate is bonded, such that the first inductor conductor and the second inductor conductor form a coil-shaped inductor.
摘要翻译：层叠电子部件包括第一层压体和包含前布线层并与第一层压体接合的第二层压体。第一层压体和第二层压体的接线层彼此正交。第一层压体具有布置在第一布线层上的第一电感器导体和布置在第二布线层上的第二电感器导体。第二层压体具有用于将第一电感器导体的端部与第二电感器导体的端部电连接到第一层压体的表面上的连接导体，使得第一电感器导体和第二电感器导体形成线圈形电感器。

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