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1. 发明授权

US06631061B2 Semiconductor integrated device 有权
标题翻译：半导体集成器件
公开(公告)号：US06631061B2
公开(公告)日：2003-10-07
申请号：US09745736
申请日：2000-12-26
申请人： Kazuhiko Okawa
发明人： Kazuhiko Okawa
IPC分类号： H02H900
CPC分类号： H01L27/0255
摘要： A semiconductor integrated device is provided which consists of a plurality of circuit blocks. Each circuit block is connected to a power supply terminal and a ground terminal. Signal interface sections connect signal circuits among the circuit blocks. A plurality of first diodes are serially connected to one another in a first direction between the ground terminal of a first one of the circuit blocks and the ground terminal of another of the circuit blocks. A plurality of second diodes are serially connected to one another in a second direction that is opposite to the first direction between the ground terminal of the first circuit block and the ground terminal of the another circuit block.
摘要翻译：提供了由多个电路块组成的半导体集成器件。每个电路块连接到电源端子和接地端子。信号接口部分在电路块之间连接信号电路。多个第一二极管在第一个电路块的接地端子和另一个电路块的接地端子之间沿第一方向彼此串联连接。多个第二二极管在与第一电路块的接地端子和另一个电路块的接地端子之间的第一方向相反的第二方向上彼此串联连接。

2. 发明授权

US06501155B2 Semiconductor apparatus and process for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06501155B2
公开(公告)日：2002-12-31
申请号：US09200424
申请日：1998-11-23
申请人： Kazuhiko Okawa
发明人： Kazuhiko Okawa
IPC分类号： H01L2358
CPC分类号： H01L27/0266 , H01L27/0259 , H01L29/0821 , H01L29/4238
摘要： To provide a semiconductor apparatus that secures high ESD protection capability and yet reduces leak current. Cut sections 64-1 and 64-2 are provided in end sections of a second edge 62 of a drain region 22. When a distance between a first edge 60 of a source region 20 and the second edge 62 in an intermediate area is defined as L1, a distance between the first edge 60 and end edges 52-1 and 52-2 of a channel stopper non-implanted region 50 is defined as L1, a relation of L2? L1 is established. By providing the channel stopper non-implanted region 50, the ESD protection capability is improved. Also, by providing the cut sections 64-1 and 64-2 in a manner to satisfy the relation that is L2 is not less than L1, leak current is reduced. The source region 20 may also be provided with a cut section. A contacts or a metal silicide layer in the drain region 22 is provided in an intermediate area being interior with respect to borders between the intermediate area and the respective end sections of the second edge 62. The present invention is also applicable to a lateral type bipolar protection circuit.
摘要翻译：提供确保高ESD保护能力并且还能够减少泄漏电流的半导体装置。在漏极区域22的第二边缘62的端部设置有部分64-1和64-2。当第一边缘60 源区域20和中间区域中的第二边缘62被定义为L1，将沟道阻挡非注入区域50的第一边缘60和端部边缘52-1和52-2之间的距离定义为L1， L2的关系？ L1建立。通过设置通道停止器非注入区域50，ESD保护能力得到改善。此外，通过以满足L2不小于L1的关系的方式设置切割部64-1和64-2，泄漏电流降低。源极区域20还可以设置有切割部分。漏区22中的触点或金属硅化物层设置在相对于第二边缘62的中间区域和相应端部之间的边界的内部的中间区域中。本发明还可应用于横向型双极保护电路。

3. 发明授权

US5345098A Master slice integrated circuit device 失效
标题翻译：主切片集成电路器件
公开(公告)号：US5345098A
公开(公告)日：1994-09-06
申请号：US878527
申请日：1992-05-05
申请人： Yasuhisa Hirabayashi , Takashi Sakuda , Kazuhiko Okawa , Yasuhiro Oguchi
发明人： Yasuhisa Hirabayashi , Takashi Sakuda , Kazuhiko Okawa , Yasuhiro Oguchi
IPC分类号： H01L21/82 , H01L21/822 , H01L23/528 , H01L27/04 , H01L27/118 , H01L27/10 , H01L27/15
CPC分类号： H01L23/5286 , H01L24/06 , H01L27/118 , H01L2224/05554 , H01L2924/14
摘要： In a master slice integrated circuit device composed of an array of internal cells having contact members, an array of external cells having contact members and formed outwardly from the internal cell array, a main power circuit region formed on the external cell array, a plurality of power lines formed on the internal array region, and a plurality of signal lines for electrically interconnecting selected contact members of the internal and external cells, intermediate power line connection regions are provided to conductively connect each power line to the main power circuit region, the intermediate connection regions including, for each power line, a power branch-off member disposed at a given position on the main power circuit region and extending substantially in the direction of its respective power line, and a connection allowance member intersecting, and connected to, the power branch-off member and having a predetermined length, the connection allowance member being conductively connected between its associated power branch-off member and the respective power line.
摘要翻译：在由具有接触构件的内部单元的阵列构成的母片集成电路器件中，具有接触构件并从内部单元阵列向外形成的外部单元的阵列，形成在外部单元阵列上的主电源电路区域，多个形成在内部阵列区域上的电力线，以及用于电连接内部和外部单元的所选接触构件的多条信号线，中间电力线连接区域，用于将每条电力线路导电连接到主电力电路区域，中间连接区域，对于每个电力线，包括设置在主电力电路区域上的给定位置并且基本上沿其相应电力线的方向延伸的电力分支构件，以及连接允许构件，其相交并连接到电力分支构件并具有预定长度，所述连接允许构件是导电的 y连接在其相关联的电力分支构件和相应的电力线之间。

4. 发明授权

US5300790A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5300790A
公开(公告)日：1994-04-05
申请号：US71348
申请日：1993-06-03
申请人： Yasuhisa Hirabayashi , Takashi Sakuda , Kazuhiko Okawa , Yasuhiro Oguchi
发明人： Yasuhisa Hirabayashi , Takashi Sakuda , Kazuhiko Okawa , Yasuhiro Oguchi
IPC分类号： H01L27/118 , H01L27/02 , H01L27/10 , H01L27/15
CPC分类号： H01L27/11807
摘要： Disclosed is a semiconductor device having complementary metal insulator semiconductor field-effect transistors (MISFETs) in which a plurality of basic cells having N-channel MOSs and P-channel MOSs are disposed. In this semiconductor device, a sub MISFET is disposed adjacently to a stopper layer in a region adjacent to other basic cell. An element such as a transmission gate composed of a single element can be actualized by use of the sub-MISFET. In the semiconductor device of this invention, a working efficiency thereof is improved. A response velocity of the P-channel MOS can also be improved using the sub-MISFET. A numerical quantity of the basic cells constituting a circuit can be reduced, resulting in a reduction in parasitic capacity. An operating time of the circuit is thereby decreased.
摘要翻译：公开了具有互补金属绝缘体半导体场效应晶体管（MISFET）的半导体器件，其中设置有多个具有N沟道MOS和P沟道MOS的基本单元。在该半导体器件中，子MISFET与邻近其他基本单元的区域中的止动层相邻设置。可以通过使用子MISFET来实现诸如由单个元件组成的传输门的元件。在本发明的半导体器件中，其工作效率提高。也可以使用子MISFET来提高P沟道MOS的响应速度。可以减少构成电路的基本单元的数量，从而降低寄生电容。因此电路的工作时间减少。

5. 发明申请

US20080224219A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080224219A1
公开(公告)日：2008-09-18
申请号：US12126473
申请日：2008-05-23
申请人： Takayuki SAIKI , Kazuhiko Okawa
发明人： Takayuki SAIKI , Kazuhiko Okawa
IPC分类号： H01L23/62
CPC分类号： H01L27/0288
摘要： A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.
摘要翻译：提供具有高性能电阻元件的半导体器件。在绝缘膜隔离的N型阱中，形成两个较高浓度的N型区域。还形成层间绝缘膜。在层间绝缘膜的多个开口中，在一个N型区域上形成具有多个电极的一个电极组，而在另一个N型区域上形成具有多个电极的第二电极组。两个N型区域之间的关系在岛状区域和围绕岛状物的环状区域之间。岛状区域和环状区域之间的N型阱的环状区域用作电阻R.因此，由于ESD等而过度施加的电荷的放电通道在一个N的周边（四个区域）中均匀地存在型区域。

6. 发明授权

US07394134B2 Semiconductor device with electrostatic discharge protection 有权
标题翻译：具有静电放电保护的半导体器件
公开(公告)号：US07394134B2
公开(公告)日：2008-07-01
申请号：US11095709
申请日：2005-03-31
申请人： Takayuki Saiki , Kazuhiko Okawa
发明人： Takayuki Saiki , Kazuhiko Okawa
IPC分类号： H01L23/62
CPC分类号： H01L27/0288
摘要： A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.
摘要翻译：提供具有高性能电阻元件的半导体器件。在绝缘膜隔离的N型阱中，形成两个较高浓度的N型区域。还形成层间绝缘膜。在层间绝缘膜的多个开口中，在一个N型区域上形成具有多个电极的一个电极组，而在另一个N型区域上形成具有多个电极的第二电极组。两个N型区域之间的关系在岛状区域和围绕岛状物的环状区域之间。岛状区域和环状区域之间的N型阱的环状区域用作电阻R.因此，由于ESD等而过度施加的电荷的放电通道在一个N的周边（四个区域）中均匀地存在型区域。

7. 发明授权

US06861705B2 Driver circuits and methods for manufacturing driver circuits 失效
标题翻译：用于制造驱动电路的驱动电路和方法
公开(公告)号：US06861705B2
公开(公告)日：2005-03-01
申请号：US09801025
申请日：2001-03-07
申请人： Satoshi Ito , Kazuhiko Okawa
发明人： Satoshi Ito , Kazuhiko Okawa
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8234 , H01L23/482 , H01L23/52 , H01L27/02 , H01L27/088 , H01L29/78
CPC分类号： H01L27/088 , H01L23/482 , H01L27/0207 , H01L2924/0002 , Y10S257/92 , H01L2924/00
摘要： Embodiments include a driver circuit that is suitable to prevent a delay in responding to an input of a drive signal and a method for manufacturing the same. Three contact holes are provided for each of the transistors Tr1-Tr4 for connecting the gate electrodes of the transistors to the signal lines Ls, Ls1-Ls4 that are separated from the transistors Tr1-Tr4 by the dielectric layer 14. As a result, the time for an input signal to reach the entire area of the gate electrodes becomes shorter and a response to an input of a drive signal becomes faster.
摘要翻译：实施例包括适于防止响应于驱动信号的输入的延迟的驱动器电路及其制造方法。为晶体管Tr1-Tr4的每一个提供三个接触孔，用于将晶体管的栅电极连接到由电介质层14与晶体管Tr1-Tr4分离的信号线Ls，Ls1-Ls4。结果，输入信号到达栅电极的整个区域的时间变短，并且对驱动信号的输入的响应变得更快。

8. 发明授权

US06653689B2 Semiconductor device having electrostatic protection circuit 有权
标题翻译：具有静电保护电路的半导体器件
公开(公告)号：US06653689B2
公开(公告)日：2003-11-25
申请号：US09873370
申请日：2001-06-05
申请人： Kazuhiko Okawa
发明人： Kazuhiko Okawa
IPC分类号： H01L2972
CPC分类号： H01L27/0262 , H01L27/0255 , H01L27/0288
摘要： A semiconductor device is provided with an electrostatic protection circuit that causes rapid breakdown of a Zener diode immediately after a static charge is applied, to discharge the static charge by a high-gain thyristor with good response characteristics, and that has a small surface area. When a static charge is applied, a Zener diode breaks down, which acts as a trigger to turn on a thyristor formed of an NPN bipolar transistor and a PNP bipolar transistor. The PNP bipolar transistor is formed of p-type, n-type, and p-type impurity diffusion regions formed in the thickness direction of the substrate and the Zener diode is formed of n-type and p-type impurity diffusion regions. An n-type impurity diffusion region is provided adjacent to a surface-layer p-type impurity diffusion region, and these p-type and n-type impurity diffusion regions are connected to a signal terminal through a silicide layer formed on the surfaces thereof.
摘要翻译：半导体器件设置有静电保护电路，其在施加静电荷之后立即引起齐纳二极管的快速击穿，以通过具有良好响应特性的高增益晶闸管对静电电荷进行放电，并具有小的表面积。当施加静电荷时，齐纳二极管发生故障，其作为触发器来接通由NPN双极晶体管和PNP双极晶体管形成的晶闸管。 PNP双极晶体管由在衬底的厚度方向上形成的p型，n型和p型杂质扩散区形成，并且齐纳二极管由n型和p型杂质扩散区形成。在表面层p型杂质扩散区域附近设置n型杂质扩散区域，这些p型杂质扩散区域和n型杂质扩散区域通过形成在其表面上的硅化物层与信号端子连接。

9. 发明授权

US06459139B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06459139B2
公开(公告)日：2002-10-01
申请号：US09727705
申请日：2000-12-04
申请人： Kunio Watanabe , Kazuhiko Okawa
发明人： Kunio Watanabe , Kazuhiko Okawa
IPC分类号： H01L2900
CPC分类号： H01L27/0251
摘要： The semiconductor device has an insulated-gate field-effect transistor (MOS transistor), a bipolar transistor, and a Zener diode. The MOS transistor is formed in a well of a first conductive type (p-type) and has a gate insulation layer, a gate electrode, side wall insulation layers, and second conductive type (n-type) of source and drain regions. The bipolar transistor has the drain region as a collector region, the well as a base region, and an n-type impurity-diffusion layer isolated from the drain region as an emitter region. The Zener diode is formed by the junction of an n-type impurity-diffusion layer continuous with the drain region and a p-type impurity-diffusion layer. The source and drain regions have a silicide layer formed on the surface thereof. A protection layer is formed on the surface of the n-type impurity-diffusion layer of the Zener diode.
摘要翻译：半导体器件具有绝缘栅场效应晶体管（MOS晶体管），双极晶体管和齐纳二极管。 MOS晶体管形成在第一导电类型（p型）的阱中，并且具有栅极绝缘层，栅电极，侧壁绝缘层和第二导电类型（n型）源极和漏极区。双极晶体管具有漏极区域作为集电极区域，阱作为基极区域，以及与漏极区域隔离的n型杂质扩散层作为发射极区域。齐纳二极管由与漏极区连续的n型杂质扩散层和p型杂质扩散层的结形成。源区和漏区在其表面上形成硅化物层。在齐纳二极管的n型杂质扩散层的表面上形成保护层。

10. 发明授权

US6046480A Protection circuit for semiconductor devices 失效
标题翻译：半导体器件保护电路
公开(公告)号：US6046480A
公开(公告)日：2000-04-04
申请号：US996204
申请日：1997-12-22
申请人： Kazuhiro Matsumoto , Kazuhiko Okawa
发明人： Kazuhiro Matsumoto , Kazuhiko Okawa
IPC分类号： H01L29/78 , H01L27/02 , H01L27/06 , H01L23/62 , H01L29/00
CPC分类号： H01L27/0255
摘要： An object is to realize a protection circuit for protecting a semiconductor device from an ESD or other surge, said protection circuit having its improved reliability with a reduced scale of circuit. An n-type diffusion region (second diffusion region) is formed on a p-type well. A diode D1 formed by the n-type diffusion region and p-type well is connected to the gate electrode of n-type transistor. Thus, the potential difference between a channel region and the gate electrode is reduced to protect the gate oxide film. The n-type diffusion region is formed in the region of the gate electrode on the side of a source region between the source region and a p-type diffusion region (second diffusion region). The layout is determined such that a bipolar formed by the drain region, p-type well and n-type diffusion region will not be turned on. A single contact of minimum size is formed in the n-type diffusion region. When it is desired to form a silicide film, it may not overlap a device isolation film. The present invention may be applied to an output buffer, input buffer, input/output buffer, interface circuit between circuits operable in different power-supply systems or the like.
摘要翻译：目的是实现用于保护半导体器件免受ESD或其他浪涌的保护电路，所述保护电路具有改进的可靠性，电路规模缩小。在p型阱上形成n型扩散区（第二扩散区）。由n型扩散区和p型阱形成的二极管D1与n型晶体管的栅极连接。因此，沟道区域和栅电极之间的电位差被减小以保护栅极氧化膜。在栅极电极的源极区域和p型扩散区域（第二扩散区域）之间的源极侧的区域中形成n型扩散区域。确定布局，使得由漏区，p型阱和n型扩散区形成的双极不会导通。在n型扩散区域中形成最小尺寸的单个接触。当需要形成硅化物膜时，其可能不与器件隔离膜重叠。本发明可以应用于可在不同电源系统等中操作的电路之间的输出缓冲器，输入缓冲器，输入/输出缓冲器，接口电路。

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