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1. 发明公开

CN106469724A 半导体装置有权
公开(公告)号：CN106469724A
公开(公告)日：2017-03-01
申请号：CN201610685667.9
申请日：2016-08-18
申请人：三星电子株式会社
发明人：拉希尔·阿兹马特 , 迪帕克·夏尔马 , 金秀贤 , 朴哲弘
IPC分类号： H01L27/092
CPC分类号： H01L27/0924 , H01L27/0207 , H01L27/092 , H01L27/11807 , H01L29/0649 , H01L29/775 , H01L2027/11859
摘要：本发明提供了一种半导体装置，该半导体装置包括：衬底，其具有第一逻辑单元、第二逻辑单元和第三逻辑单元；有源图案，其设置在第一逻辑单元至第三逻辑单元中的每一个中，以从衬底突出；以及栅极结构，其与有源图案交叉。第二逻辑单元和第三逻辑单元在第一方向上彼此间隔开，并且第一逻辑单元介于它们之间。有源图案在第一方向上排列，并且在与第一方向交叉的第二方向上延伸。当在第一方向上测量时，分别在第一逻辑单元和第二逻辑单元中的最邻近的一对有源图案之间的距离与分别在第一逻辑单元和第三逻辑单元中的最邻近的一对有源图案之间的距离不同。

2. 发明公开

CN106409831A 垂直存储器件有权
公开(公告)号：CN106409831A
公开(公告)日：2017-02-15
申请号：CN201610133440.3
申请日：2016-03-09
申请人：三星电子株式会社
发明人：黄盛珉 , 金知勇 , 边大锡
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L27/11551 , H01L27/11578 , H01L2027/11859 , H01L2027/11861
摘要：本公开提供了垂直存储器件。一种垂直存储器件包括：多个栅电极，分别在多个水平处，在基本垂直于基板的顶表面的垂直方向上彼此间隔开；沟道，在基板上在垂直方向上延伸并穿过栅电极；和多个第一接触插塞，在垂直方向上延伸并分别接触栅电极。至少一个第二接触插塞形成在该多个栅电极当中的第一栅电极上，并在垂直方向上延伸。

3. 发明公开

CN105895586A 增加共享接触孔工艺窗口的方法有权
公开(公告)号：CN105895586A
公开(公告)日：2016-08-24
申请号：CN201610317214.0
申请日：2016-05-13
申请人：武汉新芯集成电路制造有限公司
发明人：曹清晨 , 黄荣瑞
IPC分类号： H01L21/8244 , H01L27/11 , H01L27/118 , H01L21/768
CPC分类号： H01L27/1104 , H01L21/768 , H01L27/11 , H01L27/118 , H01L2027/11859
摘要：本发明提供了一种增加共享接触孔工艺窗口的方法，即对共享接触孔的版图进行修正，主要包括：首先根据共享接触孔与有源区及栅极的接触区域，将所述共享接触孔划分为两个区域；然后将所述两个区域分别沿平行于划分的方向进行扩展。本发明提供的方案中，通过将共享接触孔划分为单独的两个区域，使这两个区域可根据实际版图的状况进行修正，从而可增加共享接触孔的工艺窗口，确保所形成的共享接触孔与有源区及与栅极的连接无异常。

4. 发明授权

US08736061B2 Integrated circuits having a continuous active area and methods for fabricating same 有权
标题翻译：具有连续有效面积的集成电路及其制造方法
公开(公告)号：US08736061B2
公开(公告)日：2014-05-27
申请号：US13490840
申请日：2012-06-07
申请人： Frank Johnson , Olivier Menut , Marc Tarabbia , Gregory A. Northrop
发明人： Frank Johnson , Olivier Menut , Marc Tarabbia , Gregory A. Northrop
IPC分类号： H01L23/52
CPC分类号： H01L27/0207 , H01L23/5286 , H01L27/11807 , H01L2027/11859 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a standard cell having a first boundary, a second boundary opposite the first boundary, a third boundary interconnecting the first and second boundaries, and a fourth boundary opposite the third boundary and interconnecting the first and second boundaries. The standard cell further includes parallel active areas extending from the first boundary to the second boundary. Also, the standard cell has parallel gate strips extending from the third boundary to the fourth boundary and over the active areas. A cut mask overlies the gate strips. An interconnect is positioned overlying the cut mask and forms an electrical connection with a selected gate strip.
摘要翻译：提供了用于制造集成电路的集成电路和方法。在一个实施例中，集成电路包括具有第一边界，与第一边界相反的第二边界，互连第一和第二边界的第三边界以及与第三边界相对的第四边界并互连第一和第二边界的标准单元。标准单元还包括从第一边界延伸到第二边界的并行有效区域。此外，标准单元具有从第三边界延伸到第四边界并且在有源区上延伸的平行栅极条。切割掩模覆盖门条。互连件定位在切割掩模上方并与选定的栅条形成电连接。

5. 发明授权

US08816403B2 Efficient semiconductor device cell layout utilizing underlying local connective features 有权
标题翻译：利用潜在的本地连接特征的高效半导体器件单元布局
公开(公告)号：US08816403B2
公开(公告)日：2014-08-26
申请号：US13238294
申请日：2011-09-21
申请人： Jung-Hsuan Chen , May Chang , Chiting Cheng , Li-Chun Tien
发明人： Jung-Hsuan Chen , May Chang , Chiting Cheng , Li-Chun Tien
IPC分类号： H01L27/118 , H01L23/522
CPC分类号： H01L27/0207 , H01L2027/11859
摘要： Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.
摘要翻译：提供半导体器件单元，用于形成半导体器件单元的方法和用于半导体器件单元的布局样式。器件单元可以是整个集成电路中使用的重复单元。布局样式利用多晶硅级别的无多晶硅的区域，并且可以容纳其中或其中的导电引线。导电引线由通常用于触点或通孔的材料形成，并且设置在将器件单元彼此耦合的第一金属互连级之下。下面的局部导电引线可以形成下面的信号线，允许额外的功率网线包括在可以容纳在器件单元内并根据金属轨道设计间隔规则的有限数量的金属轨道内。

6. 发明申请

US20130328205A1 INTEGRATED CIRCUITS HAVING A CONTINUOUS ACTIVE AREA AND METHODS FOR FABRICATING SAME 有权
标题翻译：具有连续活动区域的集成电路及其制造方法
公开(公告)号：US20130328205A1
公开(公告)日：2013-12-12
申请号：US13490840
申请日：2012-06-07
申请人： Globalfoundries Inc. , International Business Machines Corporation , STMircoelectronics Inc.
发明人： Frank Johnson , Olivier Menut , Marc Tarabbia , Gregory A. Northrop
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L27/0207 , H01L23/5286 , H01L27/11807 , H01L2027/11859 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a standard cell having a first boundary, a second boundary opposite the first boundary, a third boundary interconnecting the first and second boundaries, and a fourth boundary opposite the third boundary and interconnecting the first and second boundaries. The standard cell further includes parallel active areas extending from the first boundary to the second boundary. Also, the standard cell has parallel gate strips extending from the third boundary to the fourth boundary and over the active areas. A cut mask overlies the gate strips. An interconnect is positioned overlying the cut mask and forms an electrical connection with a selected gate strip.
摘要翻译：提供了用于制造集成电路的集成电路和方法。在一个实施例中，集成电路包括具有第一边界，与第一边界相反的第二边界，互连第一和第二边界的第三边界以及与第三边界相对的第四边界并互连第一和第二边界的标准单元。标准单元还包括从第一边界延伸到第二边界的并行有效区域。此外，标准单元具有从第三边界延伸到第四边界并且在有源区上延伸的平行栅极条。切割掩模覆盖门条。互连件定位在切割掩模上方并与选定的栅条形成电连接。

7. 发明授权

US09515088B1 High density and modular CMOS logic based on 3D stacked, independent-gate, junctionless FinFETs 有权
标题翻译：基于3D堆叠，独立栅极，无结晶FinFET的高密度和模块化CMOS逻辑
公开(公告)号：US09515088B1
公开(公告)日：2016-12-06
申请号：US15040278
申请日：2016-02-10
申请人： GLOBALFOUNDRIES Inc.
发明人： Murat Kerem Akarvardar
IPC分类号： H01L27/11 , H01L27/118
CPC分类号： H01L27/11807 , H01L27/0924 , H01L27/1211 , H01L2027/11857 , H01L2027/11859
摘要： A semiconductor structure is provided with fins on a substrate, including: a first active layer with a first source, first channel, and first drain, each doped with the same concentration of dopant as each other; a dielectric layer on the first active layer; a second active layer with a second source, second channel, and second drain, each doped with the same concentration of dopant as each other; and a first and second gate disposed on an opposing first and second sidewall of the channels, respectively. A method for making such a semiconductor structure is also provided.
摘要翻译：半导体结构在衬底上设置有翅片，包括：具有第一源极，第一沟道和第一漏极的第一有源层，每个掺杂相同浓度的掺杂剂; 第一有源层上的介电层; 具有第二源极，第二沟道和第二漏极的第二有源层，每个掺杂有彼此相同浓度的掺杂物; 以及分别设置在通道的相对的第一和第二侧壁上的第一和第二门。还提供了制造这种半导体结构的方法。

8. 发明申请

US20160300851A1 SEMICONDUCTOR DEVICE INCLUDING POLYGON-SHAPED STANDARD CELL 审中-公开
标题翻译：包含多晶标准细胞的半导体器件
公开(公告)号：US20160300851A1
公开(公告)日：2016-10-13
申请号：US15095579
申请日：2016-04-11
申请人： JinTae KIM , Jaewan CHOI
发明人： JinTae KIM , Jaewan CHOI
IPC分类号： H01L27/118
CPC分类号： H01L27/11807 , G06F17/5068 , H01L27/0207 , H01L2027/11859 , H01L2027/11874 , H01L2027/11881 , H01L2027/11885
摘要： A semiconductor device including a standard cell for implementing a logic element includes a first active region and a second active region extending in a second direction on a substrate and spaced apart from each other in a first direction perpendicular to the second direction, gate electrodes intersecting the first active region and the second active region, and source regions and drain regions formed on the first and second active regions at both sides of each of the gate electrodes. A boundary of the standard cell has a polygonal shape, excluding a quadrilateral shape, when viewed in a plan view. As a result, an area of the standard cell may be reduced to reduce a size of the semiconductor device.
摘要翻译：包括用于实现逻辑元件的标准单元的半导体器件包括第一有源区和在衬底上沿第二方向延伸的第二有源区，并且在垂直于第二方向的第一方向上彼此间隔开，栅电极与第一有源区和第二有源区，以及形成在每个栅极两侧的第一和第二有源区上的源区和漏区。当在平面图中观察时，标准单元的边界具有不包括四边形形状的多边形形状。结果，可以减小标准单元的面积以减小半导体器件的尺寸。

9. 再颁专利

USRE49545E1 Semiconductor device including polygon-shaped standard cell 有权
公开(公告)号：USRE49545E1
公开(公告)日：2023-06-06
申请号：US17175381
申请日：2021-02-12
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： JinTae Kim , Jaewan Choi
IPC分类号： H01L27/118 , H01L27/02
CPC分类号： H01L27/11807 , H01L27/0207 , H01L2027/11859 , H01L2027/11874 , H01L2027/11881 , H01L2027/11885
摘要： A semiconductor device including a standard cell for implementing a logic element includes a first active region and a second active region extending in a second direction on a substrate and spaced apart from each other in a first direction perpendicular to the second direction, gate electrodes intersecting the first active region and the second active region, and source regions and drain regions formed on the first and second active regions at both sides of each of the gate electrodes. A boundary of the standard cell has a polygonal shape, excluding a quadrilateral shape, when viewed in a plan view. As a result, an area of the standard cell may be reduced to reduce a size of the semiconductor device.

10. 发明申请

US20130069236A1 EFFICIENT SEMICONDUCTOR DEVICE CELL LAYOUT UTILIZING UNDERLYING LOCAL CONNECTIVE FEATURES 有权
标题翻译：有效的半导体器件细胞布局利用本地连接特性
公开(公告)号：US20130069236A1
公开(公告)日：2013-03-21
申请号：US13238294
申请日：2011-09-21
申请人： Jung-Hsuan Chen , May Chang , Chiting Cheng , Li-Chun Tien
发明人： Jung-Hsuan Chen , May Chang , Chiting Cheng , Li-Chun Tien
IPC分类号： H01L23/52 , G06F17/50
CPC分类号： H01L27/0207 , H01L2027/11859
摘要： Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.
摘要翻译：提供半导体器件单元，用于形成半导体器件单元的方法和用于半导体器件单元的布局样式。器件单元可以是整个集成电路中使用的重复单元。布局样式利用多晶硅级别的无多晶硅的区域，并且其可以容纳其中或其中的导电引线。导电引线由通常用于触点或通孔的材料形成，并且设置在将器件单元彼此耦合的第一金属互连级之下。下面的局部导电引线可以形成下面的信号线，允许额外的功率网线被包括在可以容纳在器件单元内并根据金属轨道设计间隔规则的有限数量的金属轨道内。

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