专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5792678A Method for fabricating a semiconductor on insulator device 失效
标题翻译：半导体绝缘体器件的制造方法
公开(公告)号：US5792678A
公开(公告)日：1998-08-11
申请号：US642134
申请日：1996-05-02
申请人： Juergen A. Foerstner , Wen-Ling M. Huang , Marco Racanelli
发明人： Juergen A. Foerstner , Wen-Ling M. Huang , Marco Racanelli
IPC分类号： H01L21/84 , H01L27/12 , H01L21/8249
CPC分类号： H01L27/1203 , H01L21/84
摘要： A semiconductor on insulator structure (50) includes a silicon layer (30) formed on an insulating substrate (20). The silicon layer (30) is partitioned into two sections (32, 34) which are electrically isolated from each other. The thickness of the silicon layer (30) in a first section (32) of the silicon layer (30) is adjusted independently from the thickness of the silicon layer (30) in a second section (34) of the silicon layer (30). Independently adjusting the thickness of the silicon layer (30) allows optimizing the performance of semiconductor devices (60, 80) fabricated in the first and second sections (32, 34) of the semiconductor on insulator structure (50).
摘要翻译：半导体绝缘体结构（50）包括形成在绝缘基板（20）上的硅层（30）。硅层（30）被分隔成彼此电绝缘的两个部分（32,34）。在硅层（30）的第二部分（34）中，与硅层（30）的厚度独立地调节硅层（30）的第一部分（32）中的硅层（30）的厚度，。独立地调整硅层（30）的厚度允许优化在半导体绝缘体结构（50）的第一和第二部分（32,34）中制造的半导体器件（60,80）的性能。

2. 发明授权

US5719081A Fabrication method for a semiconductor device on a semiconductor on insulator substrate using a two stage threshold adjust implant 失效
标题翻译：使用两级阈值调整植入物在绝缘体上半导体衬底上的半导体器件的制造方法
公开(公告)号：US5719081A
公开(公告)日：1998-02-17
申请号：US552656
申请日：1995-11-03
申请人： Marco Racanelli , Wen-Ling M. Huang , Bor-Yuan C. Hwang , Juergen A. Foerstner
发明人： Marco Racanelli , Wen-Ling M. Huang , Bor-Yuan C. Hwang , Juergen A. Foerstner
IPC分类号： H01L21/336 , H01L29/10 , H01L29/786
CPC分类号： H01L29/78696 , H01L29/105 , H01L29/66772 , H01L29/78609 , H01L29/78621
摘要： A two stage threshold adjust implantation process is performed after field oxidation to avoid the effects of dopant redistribution and segregation. At any of several steps in a manufacturing process, only routine implant energy and dose adjustments are required to create a first and a second dopant profile (110, 120) that result in the reduction of edge leakage and threshold voltage sensitivity to device layer thickness of a semiconductor device on a semiconductor on insulator substrate.
摘要翻译：在场氧化后进行两级阈值调整注入工艺，以避免掺杂剂再分布和分离的影响。在制造过程中的几个步骤中的任何一个步骤中，仅需要常规的植入能量和剂量调整以产生第一和第二掺杂剂分布（110,120），其导致边缘泄漏的减小和对器件层厚度的阈值电压敏感性半导体衬底上的半导体器件。

3. 发明授权

US5532175A Method of adjusting a threshold voltage for a semiconductor device fabricated on a semiconductor on insulator substrate 失效
标题翻译：调制半导体器件的绝缘体上半导体器件的阈值电压的方法
公开(公告)号：US5532175A
公开(公告)日：1996-07-02
申请号：US423614
申请日：1995-04-17
申请人： Marco Racanelli , Bor-Yuan C. Hwang , Juergen Foerstner , Wen-Ling M. Huang
发明人： Marco Racanelli , Bor-Yuan C. Hwang , Juergen Foerstner , Wen-Ling M. Huang
IPC分类号： H01L27/092 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/00 , H01L29/786 , H01L21/335
CPC分类号： H01L29/78627 , H01L29/66772 , H01L29/78621 , H01L29/78696 , Y10S148/15
摘要： A method of adjusting a threshold voltage for a semiconductor device on a semiconductor on insulator substrate includes performing a threshold voltage adjustment implant (25) after formation of a gate structure (16) to reduce the diffusion of implanted dopant (26). Reducing dopant diffusion eliminates the narrow channel effect which degrades device performance. Implanting the dopant (26) after formation of the gate structure (16) simplifies processing of semiconductor device (28) by eliminating a photolithography step which is accomplished by utilizing photoresist (21) used for a source and drain implant (22).
摘要翻译：在半导体绝缘体衬底上调整半导体器件的阈值电压的方法包括在形成栅极结构（16）之后执行阈值电压调整注入（25）以减少注入的掺杂剂（26）的扩散。减少掺杂剂扩散消除了窄通道效应，这降低了器件性能。在形成栅极结构（16）之后，注入掺杂剂（26）通过消除通过利用用于源极和漏极注入（22）的光致抗蚀剂（21）来实现的光刻步骤来简化半导体器件（28）的处理。

4. 发明授权

US5374568A Method for forming a base link in a bipolar transistor 失效
标题翻译：在双极晶体管中形成基极连接的方法
公开(公告)号：US5374568A
公开(公告)日：1994-12-20
申请号：US125986
申请日：1993-09-23
申请人： Wen-Ling M. Huang , Shrinath Ramaswami , Maureen F. Grimaldi
发明人： Wen-Ling M. Huang , Shrinath Ramaswami , Maureen F. Grimaldi
IPC分类号： H01L21/331 , H01L21/8249 , H01L29/10 , H01L29/73 , H01L21/265
CPC分类号： H01L29/66265 , H01L21/8249 , H01L29/1008 , H01L29/7317 , Y10S148/01
摘要： A method for forming an improved base link for a bipolar transistor is provided. The wall where the base link (44) is formed is substantially vertical (32,34). An oxide mask (24) is use during etching of the polysilicon layer (18) that provides the wall, instead of a conventional photoresist mask. The preferred method is compatible with manufacturing BiCMOS devices.
摘要翻译：提供了一种用于形成用于双极晶体管的改进的基极连接的方法。形成基部连接件（44）的壁基本垂直（32,34）。在蚀刻提供壁的多晶硅层（18）期间使用氧化物掩模（24），而不是传统的光致抗蚀剂掩模。优选的方法与制造BiCMOS器件兼容。

5. 发明授权

US5008210A Process of making a bipolar transistor with a trench-isolated emitter 失效
标题翻译：制造具有沟槽隔离发射极的双极晶体管的工艺
公开(公告)号：US5008210A
公开(公告)日：1991-04-16
申请号：US510637
申请日：1990-04-18
申请人： Shang-yi Chiang , Wen-Ling M. Huang , Clifford I. Drowley , Paul V. Voorde
发明人： Shang-yi Chiang , Wen-Ling M. Huang , Clifford I. Drowley , Paul V. Voorde
IPC分类号： H01L21/331 , H01L29/06 , H01L29/10 , H01L29/732
CPC分类号： H01L29/66272 , H01L29/0649 , H01L29/1004 , H01L29/732 , Y10S148/011
摘要： This invention pertains to a self-aligned trench-isolated emitter structure and the method for forming same. The emitter structure comprises a portion of a bipolar transistor which exhibits improved function due to the emitter structure. A single layer of conductive material forms both the emitter and base contacts in the transistor structure, which structure has particularly shallow emitter and base junctions (about 0.15 micrometer or less). The self-aligned emitter contact, isolated from the base contact by a dielectric filled trench, permits overall size reduction of the device, whereby junction area and accompanying leakage across junctions is reduced. In addition, when the structure of the bipolar transistor is such that the trench isolates the emitter area from both the base contact and the extrinsic base, it is possible to provide improved base conductivity without generating peripheral transistor effects. The bipoloar transistor can be either N-P-N type or P-N-P type depending on the materials of fabrication, although high speed devices are typically of the N-P-N type. The method includes forming a sidewall spacer (246), creating an etch-masking layer (250), removing the spacer, and etching an isolation trench at the location previously occupied by the spacer.
摘要翻译：本发明涉及自对准沟槽隔离发射极结构及其形成方法。发射极结构包括双极晶体管的一部分，其由于发射极结构而表现出改善的功能。单层导电材料在晶体管结构中形成发射极和基极触点，该结构具有特别浅的发射极和基极结（约0.15微米或更小）。通过介质填充的沟槽与基极接触隔离的自对准发射极接触允许器件的整体尺寸减小，从而降低了接合面积和相邻的接合泄漏。此外，当双极晶体管的结构使得沟槽将发射极区域与基极接触和非本征基极隔离时，可以提供改进的基极导电性而不产生周边晶体管效应。尽管高速器件通常是N-P-N型，但双酚晶体管可以是N-P-N型或P-N-P型，这取决于制造材料。该方法包括形成侧壁间隔物（246），产生蚀刻掩模层（250），去除间隔物，以及在先前由间隔物占据的位置处蚀刻隔离沟槽。

6. 发明申请

US20150277563A1 DYNAMIC TACTILE USER INTERFACE 审中-公开
标题翻译：动态触觉用户界面
公开(公告)号：US20150277563A1
公开(公告)日：2015-10-01
申请号：US14229577
申请日：2014-03-28
申请人： Wen-Ling M. Huang , Giuseppe Raffa , Glen J. Anderson
发明人： Wen-Ling M. Huang , Giuseppe Raffa , Glen J. Anderson
IPC分类号： G06F3/01 , G06F3/0487
CPC分类号： G06F3/016 , G06F1/1694 , G06F3/041 , G06F2203/0383
摘要： Systems and methods may provide for a programmable array of tactile elements in which the active elements may be dynamically altered in time and space and in dependence upon the orientation of the device of which it is a part. That device may be part of a wearable device, such as a hat, smart watch, smart glasses, glove, wristband or other garment.
摘要翻译：系统和方法可以提供可触发元件的可编程阵列，其中有源元件可以在时间和空间上动态地改变，并且依赖于其作为其一部分的装置的取向。该装置可以是可穿戴装置的一部分，例如帽子，智能手表，智能眼镜，手套，腕带或其他服装。

7. 发明授权

US5144403A Bipolar transistor with trench-isolated emitter 失效
标题翻译：具有沟槽隔离发射极的双极晶体管
公开(公告)号：US5144403A
公开(公告)日：1992-09-01
申请号：US595725
申请日：1990-10-09
申请人： Shang-yi Chiang , Wen-Ling M. Huang , Clifford I. Drowley , Paul V. Voorde
发明人： Shang-yi Chiang , Wen-Ling M. Huang , Clifford I. Drowley , Paul V. Voorde
IPC分类号： H01L21/331 , H01L29/06 , H01L29/10 , H01L29/732
CPC分类号： H01L29/66272 , H01L29/0649 , H01L29/1004 , H01L29/732
摘要： This invention pertains to a self-aligned, trench-isolated emitter structure and the method for forming same. The emitter structure comprises a portion of a bipolar transistor which exhibits improved function due to the emitter structure. A single layer of conductive material forms both the emitter and base contacts in the transistor structure, which structure has particularly shallow emitter and base junctions (about 0.15 micrometer or less). The self-aligned emitter contact, isolated from the base contact by a dielectric filled trench, permits overall size reduction of the device, whereby junction area and accompanying leakage across junctions is reduced. In addition, when the structure of the bipolar transistor is such that the trench isolates the emitter area from both the base contact and the extrinsic base, it is possible to provide improved base conductivity without generating peripheral transistor effects. The bipolar transistor can be either N-P-N type or P-N-P type depending on the materials of fabrication, although high speed devices are typically of the N-P-N type.
摘要翻译：本发明涉及自对准，沟槽隔离的发射极结构及其形成方法。发射极结构包括双极晶体管的一部分，其由于发射极结构而表现出改善的功能。单层导电材料在晶体管结构中形成发射极和基极触点，该结构具有特别浅的发射极和基极结（约0.15微米或更小）。通过介质填充的沟槽与基极接触隔离的自对准发射极接触允许器件的整体尺寸减小，从而降低了接合面积和相邻的接合泄漏。此外，当双极晶体管的结构使得沟槽将发射极区域与基极接触和非本征基极隔离时，可以提供改进的基极导电性而不产生周边晶体管效应。尽管高速器件通常是N-P-N型，但双极晶体管可以是N-P-N型或P-N-P型，这取决于制造材料。

8. 发明申请

US20150052239A1 CONTEXT BASED SPECTRUM MANAGEMENT SYSTEM 审中-公开
标题翻译：基于上下文的频谱管理系统
公开(公告)号：US20150052239A1
公开(公告)日：2015-02-19
申请号：US13969821
申请日：2013-08-19
申请人： Anthony G. Lamarca , Vallabhajosyula S. Somayazulu , Xue Yang , Denver H. Dash , Kerstin Johnsson , Jaideep Moses , Wen-Ling M. Huang , Omesh Tickoo , Jeffrey R. Foerster , Carlos Cordeiro , Christian Maciocco , Harry G. Skinner , Geoff O. Weaver , Xingang Guo , Maynard C. Falconer , Rahul C. Shah , Srikathyayani Srikanteswara
发明人： Anthony G. Lamarca , Vallabhajosyula S. Somayazulu , Xue Yang , Denver H. Dash , Kerstin Johnsson , Jaideep Moses , Wen-Ling M. Huang , Omesh Tickoo , Jeffrey R. Foerster , Carlos Cordeiro , Christian Maciocco , Harry G. Skinner , Geoff O. Weaver , Xingang Guo , Maynard C. Falconer , Rahul C. Shah , Srikathyayani Srikanteswara
IPC分类号： H04L12/26
CPC分类号： H04L12/1485 , H04L41/5029 , H04W4/24 , H04W28/20
摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for context based spectrum management. A device may include a user preference determination module to determine a level-of-service preference of a user of the device, the preference associated with an application. The device may also include a user state determination module, to determine a state of the user, and a device capability determination module, to determine capabilities of the device. The device may further include an application programming interface (API) to provide the context to a cloud-based server configured to manage spectrum. The context includes the preference, the state and the capabilities. The API is further configured to receive content delivery options from the cloud-based server.
摘要翻译：通常，本公开提供了用于基于上下文的频谱管理的系统，设备，方法和计算机可读介质。设备可以包括用户偏好确定模块，用于确定设备的用户的服务等级偏好，与应用相关联的偏好。设备还可以包括用于确定用户的状态的用户状态确定模块和设备能力确定模块，以确定设备的能力。该设备还可以包括应用程序编程接口（API），以将上下文提供给配置为管理频谱的基于云的服务器。上下文包括偏好，状态和功能。该API还被配置为从基于云的服务器接收内容传递选项。

9. 发明授权

US5656844A Semiconductor-on-insulator transistor having a doping profile for fully-depleted operation 失效
标题翻译：具有用于完全耗尽操作的掺杂分布的绝缘体上半导体晶体管
公开(公告)号：US5656844A
公开(公告)日：1997-08-12
申请号：US507898
申请日：1995-07-27
申请人： Kevin M. Klein , Wen-Ling M. Huang , Jun Ma
发明人： Kevin M. Klein , Wen-Ling M. Huang , Jun Ma
IPC分类号： H01L21/336 , H01L29/786 , H01L27/01 , H01L27/12 , H01L29/76
CPC分类号： H01L29/78696 , H01L29/66772 , H01L29/78612 , H01L29/78657
摘要： A semiconductor-on-insulator transistor (10) has a channel region (30) in a semiconductor film (16) under a gate insulating layer (26). The channel region has a top dopant concentration N.sub.T at a top surface (32) of the film that is significantly greater than a bottom dopant concentration N.sub.B at a bottom surface (34) of the film. This non-uniform doping profile provides an SOI device that operates in a fully-depleted mode, yet permits thicker films without a significant degradation of sub-threshold slope.
摘要翻译：绝缘体上半导体晶体管（10）在栅极绝缘层（26）下方的半导体膜（16）中具有沟道区（30）。沟道区在薄膜的顶表面（32）处具有明显大于薄膜底表面（34）处的底部掺杂剂浓度NB的顶部掺杂剂浓度NT。这种非均匀掺杂分布提供了以完全耗尽模式工作的SOI器件，但允许较厚的膜，而不会明显降低子阈值斜率。

10. 发明授权

US5121184A Bipolar transistor containing a self-aligned emitter contact and method for forming transistor 失效
标题翻译：包含自对准发射极接触的双极晶体管和用于形成晶体管的方法
公开(公告)号：US5121184A
公开(公告)日：1992-06-09
申请号：US664685
申请日：1991-03-05
申请人： Wen-Ling M. Huang , Kristin Brigham
发明人： Wen-Ling M. Huang , Kristin Brigham
IPC分类号： H01L29/73 , H01L21/331 , H01L21/768 , H01L23/532 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/76834 , H01L21/76897 , H01L23/53271 , H01L29/7322 , H01L2924/0002
摘要： In a process for fabricating a bipolar transistor with a single polysilicon layer, a silicon nitride layer 22 and a phospho-silicate glass layer 24 are formed on top of the polysilicon layer and the link oxide layers. The glass layer 24 has a high etch selectivity compared to the nitride layer 22 so that the glass layer may be overetched above the emitter polysilicon region without overetching the link oxide. The nitride layer is then removed by etching without significantly affecting the link oxide layer. Thus the emitter metal contact may be self-aligned on top of the emitter polysilicon region 14, 114.
摘要翻译：在制造具有单个多晶硅层的双极晶体管的工艺中，在多晶硅层和连接氧化物层的顶部上形成氮化硅层22和磷硅酸盐玻璃层24。与氮化物层22相比，玻璃层24具有高的蚀刻选择性，使得玻璃层可以在发射极多晶硅区域上方过蚀刻，而不会过氧化连接氧化物。然后通过蚀刻去除氮化物层，而不显着影响环氧化物层。因此，发射极金属接触可以在发射极多晶硅区域14,114的顶部自对准。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式