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1. 发明授权

US07732324B2 Semiconductor device having improved adhesion and reduced blistering between etch stop layer and dielectric layer 有权
标题翻译：半导体器件具有改善的粘附性并减少蚀刻停止层和电介质层之间的起泡
公开(公告)号：US07732324B2
公开(公告)日：2010-06-08
申请号：US11961464
申请日：2007-12-20
申请人： Ju-Ai Ruan , Sameer K. Ajmera , Changming Jin , Anand J. Reddy , Tae S. Kim
发明人： Ju-Ai Ruan , Sameer K. Ajmera , Changming Jin , Anand J. Reddy , Tae S. Kim
IPC分类号： H01L21/469
CPC分类号： H01L23/53295 , H01L21/76832 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).
摘要翻译：本发明的一个方面提供了形成半导体器件（100）的方法。一个方面包括在半导体衬底（105）上形成晶体管（120,125），在晶体管（120,125）之上形成第一层间电介质层（165），并在第一层间电介质内形成金属互连（170,175）层（165）。使用含碳气体在沉积工具内的金属互连（170,175）和第一层间介电层（165）上形成氮化硅（SiCN）层（180）。通过中断沉积室内的含碳气体的流动，在沉积工具内在SiCN层（180）上形成粘附层（185）。第二层间介质层（190）形成在粘合层（185）上方。

2. 发明申请

US20060081965A1 Plasma treatment of an etch stop layer 审中-公开
标题翻译：蚀刻停止层的等离子体处理
公开(公告)号：US20060081965A1
公开(公告)日：2006-04-20
申请号：US10966506
申请日：2004-10-15
申请人： Ju-Ai Ruan , Qi-Zhong Hong , Zhijian Lu
发明人： Ju-Ai Ruan , Qi-Zhong Hong , Zhijian Lu
IPC分类号： H01L23/58 , H01L21/42
CPC分类号： H01L21/0217 , H01L21/02115 , H01L21/0234 , H01L21/3105 , H01L21/3148 , H01L21/318 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L23/3171 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing an etch stop layer 18, 20, 21 on a semiconductor wafer 2 and the etch stop layer 18, 20, 21 produced by the method. The method includes depositing a dielectric layer 18, 20, 21 and applying a plasma treatment to the semiconductor wafer 2. Also, an etch stop layer 18, 20, 21 on a semiconductor wafer 2 having a modified surface and an amine deficient bulk.
摘要翻译：在半导体晶片2上制造蚀刻停止层18,20,21的方法和通过该方法制造的蚀刻停止层18,20,21。该方法包括沉积电介质层18,20,21并对半导体晶片2施加等离子体处理。而且，具有改性表面和胺缺乏体积的半导体晶片2上的蚀刻停止层18,20,21。

3. 发明申请

US20050241672A1 Extraction of impurities in a semiconductor process with a supercritical fluid 审中-公开
标题翻译：用超临界流体萃取半导体工艺中的杂质
公开(公告)号：US20050241672A1
公开(公告)日：2005-11-03
申请号：US10917772
申请日：2004-08-13
申请人： Phillip Matz , Sameer Ajmera , Ju-Ai Ruan , Jinyoung Kim , Zhijian Lu , Laura Matz
发明人： Phillip Matz , Sameer Ajmera , Ju-Ai Ruan , Jinyoung Kim , Zhijian Lu , Laura Matz
IPC分类号： B08B6/00 , B08B7/00 , H01L21/02 , H01L21/3105
CPC分类号： H01L21/3105 , B08B7/0021 , H01L21/02101
摘要： A method comprises extracting impurities from one or more materials in a semiconductor device via treatment with a supercritical fluid (SCF). The SCF may comprise a solvent and one or more co-solvents. Solvents may comprise 1-hexanol, 1-propanol, 2-propanol, acetone, ammonia, argon, carbon dioxide, chlorotrifluoromethane, cyclohexane, dichlorodifluoromethane, ethane, ethyl alcohol, ethylene, methane, methanol, n-butane, n-hexane, nitrous oxide, n-pentane, propane, propylene, toluene, trichlorofluoromethane, trichloromethane, water, or combinations thereof.
摘要翻译：一种方法包括通过用超临界流体（SCF）处理从半导体器件中的一种或多种材料中提取杂质。 SCF可以包含溶剂和一种或多种共溶剂。溶剂可以包括1-己醇，1-丙醇，2-丙醇，丙酮，氨，氩气，二氧化碳，三氟甲烷，环己烷，二氯二氟甲烷，乙烷，乙醇，乙烯，甲烷，甲醇，正丁烷，正己烷，亚硝酸氧化物，正戊烷，丙烷，丙烯，甲苯，三氯氟甲烷，三氯甲烷，水或其组合。

4. 发明授权

US09052507B1 Micro-electro-mechanical motion transducer 有权
标题翻译：微机电运动传感器
公开(公告)号：US09052507B1
公开(公告)日：2015-06-09
申请号：US13764798
申请日：2013-02-12
申请人： Ju-Ai Ruan
发明人： Ju-Ai Ruan
IPC分类号： H02N1/00 , G02B26/00 , G02B26/02
CPC分类号： G02B26/02 , B81B3/0021 , B81B2201/047 , B81B2203/051
摘要： A novel method of modulating the motion or displacement of function units in MEMS (micro-electro-mechanical-system) devices (or MEMS motion transducers) is described. This method generates small vertical displacement of one MEMS component (activation component) in the device and effectively translates that displacement into the displacement of another MEMS component (function unit) in the same device in an in-plan direction that is perpendicular to the direction of the vertical displacement of activation component. The activation component has a large surface area of electrostatic interaction with its interacting electrode, capable of generating large activation force at small voltages. Therefore this method makes it effective to modulate the motion or displacement of the function unit of MEMS motion transducers in an in-plan direction at low voltages. Specific designs of MEMS motion transducers employing this method are disclosed.
摘要翻译：描述了一种调制MEMS（微电子机械系统）装置（或MEMS运动换能器）中的功能单元的运动或位移的新颖方法。该方法在装置中产生一个MEMS部件（激活部件）的小的垂直位移，并将该位移有效地平移在同一装置中的另一个MEMS部件（功能单元）的位移，该平行方向垂直于激活组件的垂直位移。活化组分具有与其相互作用的电极的静电相互作用的大的表面积，能够在小电压下产生大的活化力。因此，这种方法可以有效地在低电压下调制MEMS运动传感器的功能单元在平面方向上的运动或位移。公开了采用该方法的MEMS运动传感器的具体设计。

5. 发明授权

US07995263B1 Transmission and reflection dual operational mode light processing device 有权
标题翻译：传输和反射双操作模式光处理装置
公开(公告)号：US07995263B1
公开(公告)日：2011-08-09
申请号：US12317603
申请日：2008-12-26
申请人： Ju-Ai Ruan
发明人： Ju-Ai Ruan
IPC分类号： G02B26/00
CPC分类号： G02B26/02
摘要： A spatial light modulator suitable for flat panel displays and methods of making the modulators are disclosed. The light modulator comprises a light separator, integrated circuits (IC), light switches (concurrently called light shutters), and optional color filters. The light separator is used to direct light uniformly illuminated on the incident surface (entrance surface) into individual pixels, and condenses the light within each pixel to a small fraction of pixel space on the viewing surface. ICs and light shutters are used to control color and light intensity at individual pixels. Several novel designs of the light modulator and light shutters are disclosed. Methods of building self-aligned structures for placing micro-spherical ball spacers for attaching protective screens to the light modulator is also disclosed.
摘要翻译：公开了适用于平板显示器的空间光调制器和制造调制器的方法。光调制器包括光分离器，集成电路（IC），光开关（同时称为光闸）和可选的滤色器。光分离器用于将均匀地照射在入射表面（入射面）上的光引导到单独的像素中，并且将每个像素内的光聚焦到观察表面上的一小部分像素空间。 IC和光闸用于控制各个像素的颜色和光强度。公开了光调制器和光闸的若干新颖设计。还公开了用于将用于将防护屏幕附着到光调制器的微球形球隔离件的自对准结构的方法。

6. 发明申请

US20080150131A1 SEMICONDUCTOR DEVICE MANUFACTURED BY REDUCING HILLOCK FORMATION IN METAL INTERCONNECTS 有权
标题翻译：通过减少金属互连中的HILLOCK形成制造的半导体器件
公开(公告)号：US20080150131A1
公开(公告)日：2008-06-26
申请号：US11614511
申请日：2006-12-21
申请人： Ju-Ai Ruan , Changming Jin , Sopa Chevacharoenkul , Satyavolu Papa Rao , Tae Seung Kim
发明人： Ju-Ai Ruan , Changming Jin , Sopa Chevacharoenkul , Satyavolu Papa Rao , Tae Seung Kim
IPC分类号： H01L21/768 , H01L23/52
CPC分类号： H01L21/02074 , H01L21/76883 , Y10S438/937
摘要： A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.
摘要翻译：一种制造互连结构的方法，包括将空的沉积室暴露于在等离子体存在下产生由源气体产生的反应物质的方法。该方法还包括终止等离子体，然后将其上的金属层的半导体衬底引入室中，同时反应物质存在于室中。

7. 发明授权

US06790777B2 Method for reducing contamination, copper reduction, and depositing a dielectric layer on a semiconductor device 有权
公开(公告)号：US06790777B2
公开(公告)日：2004-09-14
申请号：US10288717
申请日：2002-11-06
申请人： Glenn J. Tessmer , Ju-Ai Ruan , Mercer Lusk Brugler , Sarah Hartwig
发明人： Glenn J. Tessmer , Ju-Ai Ruan , Mercer Lusk Brugler , Sarah Hartwig
IPC分类号： H01L2144
CPC分类号： H01L21/76834 , Y10S438/906 , Y10S438/913 , Y10S438/974
摘要： The present invention relates to a method for improving an interface of a semiconductor device. The method comprises providing a first and second substrate having an oxidized region, and establishing a first loading position in a first process chamber. The first and second substrates are consecutively inserted into the first process chamber and generally simultaneously processed, wherein the oxidized region is reduced by exposure to a first plasma. The first and second substrates are then consecutively removed and the first substrate is inserted into a second process chamber and subsequently processed. The second substrate is then inserted into the second process chamber and the first and second substrates are simultaneously processed. The first substrate is the removed, and the second substrate is processed again. According to one exemplary aspect, the first and second substrates are exposed to a first temperature in the first process chamber for approximately half the time the first and second substrates are exposed to a higher second temperature in the second process chamber while maintaining throughput of substrates.

8. 发明授权

US06686283B1 Shallow trench isolation planarization using self aligned isotropic etch 有权
标题翻译：使用自对准各向同性蚀刻的浅沟槽隔离平面化
公开(公告)号：US06686283B1
公开(公告)日：2004-02-03
申请号：US09498083
申请日：2000-02-04
申请人： Shawn T. Walsh , John E. Campbell , Somit Joshi , James B. Friedmann , Michael J. McGranaghan , Janice D. Makos , Arun Sivasothy , Troy A. Yocum , Jaideep Mavoori , Wayne A. Bather , Joe G. Tran , Ju-Ai Ruan , Michelle L. Hartsell , Gregory B. Shinn
发明人： Shawn T. Walsh , John E. Campbell , Somit Joshi , James B. Friedmann , Michael J. McGranaghan , Janice D. Makos , Arun Sivasothy , Troy A. Yocum , Jaideep Mavoori , Wayne A. Bather , Joe G. Tran , Ju-Ai Ruan , Michelle L. Hartsell , Gregory B. Shinn
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/31056
摘要： A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.
摘要翻译：一种用于形成用于集成电路的平面隔离结构的方法。在隔离填充材料上形成蚀刻阻挡层，并且执行回蚀以去除衬底的未蚀刻部分上方的材料。将暴露的填充材料蚀刻并平坦化以形成平面隔离结构。

9. 发明授权

US07745335B2 Semiconductor device manufactured by reducing hillock formation in metal interconnects 有权
标题翻译：通过减少金属互连中的小丘形成制造的半导体器件
公开(公告)号：US07745335B2
公开(公告)日：2010-06-29
申请号：US11614511
申请日：2006-12-21
申请人： Ju-Ai Ruan , Changming Jin , Sopa Chevacharoenkul , Satyavolu Papa Rao , Tae Seung Kim
发明人： Ju-Ai Ruan , Changming Jin , Sopa Chevacharoenkul , Satyavolu Papa Rao , Tae Seung Kim
IPC分类号： H01L21/4763 , H01L21/44 , B05D3/00
CPC分类号： H01L21/02074 , H01L21/76883 , Y10S438/937
摘要： A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.
摘要翻译：一种制造互连结构的方法，包括将空的沉积室暴露于在等离子体存在下产生由源气体产生的反应物质的方法。该方法还包括终止等离子体，然后将其上的金属层的半导体衬底引入室中，同时反应物质存在于室中。

10. 发明申请

US20080057711A1 Reduction of punch-thru defects in damascene processing 有权
标题翻译：减少镶嵌加工中的穿孔缺陷
公开(公告)号：US20080057711A1
公开(公告)日：2008-03-06
申请号：US11511698
申请日：2006-08-29
申请人： Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
发明人： Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
IPC分类号： H01L21/44
CPC分类号： H01L21/76834 , H01L21/02063 , H01L21/02164 , H01L21/02274 , H01L21/02282 , H01L21/31116 , H01L21/31608 , H01L21/31625 , H01L21/76802 , H01L21/76814 , H01L21/76883
摘要： A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.
摘要翻译：制造半导体器件，同时减轻金属化层中的导电空隙形成。提供基板。第一电介质层形成在衬底上。在第一电介质层内形成导电沟槽。在第一介电层上形成蚀刻停止层。在蚀刻停止层上/上形成第二介电层。在器件上形成抗蚀剂掩模，并且在第二介电层中蚀刻通孔。抗蚀剂掩模通过灰过程去除。执行清洁处理，其减轻/减少蚀刻停止层的暴露部分上的表面电荷。采用附加的表面电荷还原技术。通孔开口填充有导电材料，并执行平面化处理以去除多余的填充材料。

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