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1. 发明授权

US06877667B1 Integrated circuit and associated design method with antenna error control using spare gates 有权
标题翻译：集成电路及相关设计方法，采用备用门控进行天线误差控制
公开(公告)号：US06877667B1
公开(公告)日：2005-04-12
申请号：US10640804
申请日：2003-08-13
申请人： Jay H. Angle , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
发明人： Jay H. Angle , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
IPC分类号： G06F17/50 , G06K19/06 , H01L21/8238 , H01L27/118
CPC分类号： G06F17/5068 , H01L27/11807
摘要： Antenna errors are corrected in an integrated circuit design utilizing spare gates distributed throughout the integrated circuit. An integrated circuit in accordance with the invention includes standard cells interspersed with spare gates. For example, the circuit may include one or more rows of spare gates arranged between groups of rows of standard cells, or islands of spare gates arranged between groups of rows of standard cells. A signal line of the integrated circuit having a detected antenna error associated therewith is coupled via one or more conductors associated with at least one metal layer of the integrated circuit to a diode or other antenna error control circuitry formed using at least one of the spare gates. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool. The coupling of the signal line having the detected antenna error associated therewith to the antenna error control circuitry formed using at least one of the spare gates is preferably determined as part of a routing operation of the automated place and route process of the standard cell CAD tool. The spare gates are preferably implemented as spare gate cells using a base transistor structure compatible with the standard cell CAD tool.
摘要翻译：在利用分布在整个集成电路中的备用门的集成电路设计中校正天线误差。根据本发明的集成电路包括散布有备用门的标准单元。例如，电路可以包括布置在标准单元行的行之间的一行或多行备用门，或者排列在标准单元行的组之间的备用栅岛。具有与其相关联的检测到的天线误差的集成电路的信号线经由与集成电路的至少一个金属层相关联的一个或多个导体耦合到使用至少一个备用栅极形成的二极管或其他天线误差控制电路。标准电池和备用门优选地根据标准电池计算机辅助设计（CAD）工具的自动化位置和路线过程的放置操作放置。具有与之相关的检测到的天线误差的信号线与使用至少一个备用门形成的天线误差控制电路的耦合优选地被确定为标准单元CAD工具的自动化位置和路线过程的路由操作的一部分。备用门优选地实现为使用与标准单元CAD工具兼容的基本晶体管结构的备用栅极单元。

2. 发明授权

US06814296B2 Integrated circuit and associated design method with antenna error control using spare gates 失效
标题翻译：集成电路及相关设计方法，采用备用门控进行天线误差控制
公开(公告)号：US06814296B2
公开(公告)日：2004-11-09
申请号：US10135308
申请日：2002-04-30
申请人： Jay H. Angle , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
发明人： Jay H. Angle , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
IPC分类号： G06K1906
CPC分类号： G06F17/5068 , H01L27/11807
摘要： Antenna errors are corrected in an integrated circuit design utilizing spare gates distributed throughout the integrated circuit. An integrated circuit in accordance with the invention includes standard cells interspersed with spare gates. For example, the circuit may include one or more rows of spare gates arranged between groups of rows of standard cells, or islands of spare gates arranged between groups of rows of standard cells. A signal line of the integrated circuit having a detected antenna error associated therewith is coupled via one or more conductors associated with at least one metal layer of the integrated circuit to a diode or other antenna error control circuitry formed using at least one of the spare gates. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool. The coupling of the signal line having the detected antenna error associated therewith to the antenna error control circuitry formed using at least one of the spare gates is preferably determined as part of a routing operation of the automated place and route process of the standard cell CAD tool. The spare gates are preferably implemented as spare gate cells using a base transistor structure compatible with the standard cell CAD tool.
摘要翻译：在利用分布在整个集成电路中的备用门的集成电路设计中校正天线误差。根据本发明的集成电路包括散布有备用门的标准单元。例如，电路可以包括布置在标准单元行的行之间的一行或多行备用门，或者排列在标准单元行的组之间的备用栅岛。具有与其相关联的检测到的天线误差的集成电路的信号线经由与集成电路的至少一个金属层相关联的一个或多个导体耦合到使用至少一个备用栅极形成的二极管或其他天线误差控制电路。标准电池和备用门优选地根据标准电池计算机辅助设计（CAD）工具的自动化位置和路线过程的放置操作放置。具有与之相关的检测到的天线误差的信号线与使用至少一个备用门形成的天线误差控制电路的耦合优选地被确定为标准单元CAD工具的自动化位置和路线过程的路由操作的一部分。备用门优选地实现为使用与标准单元CAD工具兼容的基本晶体管结构的备用栅极单元。

3. 发明授权

US06822477B1 Integrated circuit and associated design method using spare gate islands 有权
标题翻译：使用备用栅极岛的集成电路和相关设计方法
公开(公告)号：US06822477B1
公开(公告)日：2004-11-23
申请号：US10600042
申请日：2003-06-20
申请人： Craig Bingert , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
发明人： Craig Bingert , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
IPC分类号： H03K19117
CPC分类号： H01L27/11807
摘要： An integrated circuit includes standard cells interspersed with islands of spare gates. The spare gates are arranged in multiple groups of spare gates, with each group of spare gates within a corresponding designated spare gate area of a standard cell portion of the integrated circuit. At least a given one of the groups of spare gates is arranged between first and second rows of the standard cells and includes one or more rows of spare gates. The spare gate islands may be distributed throughout the standard cell portion of the integrated circuit in a substantially uniform manner, for example, in accordance with a predetermined geometric pattern. The spare gates may be converted to active gates in conjunction with the automated place and route process using only conductors in one or more metal layers of the integrated circuit.
摘要翻译：集成电路包括散布有备用栅极岛的标准单元。备用门被布置在多组备用门中，每组备用门位于集成电路的标准单元部分的对应的指定备用栅极区域内。这些备用门组中的至少一个组被布置在标准单元的第一行和第二行之间，并且包括一行或多行备用门。备用栅极岛可以以基本上均匀的方式分布在集成电路的整个标准单元部分，例如根据预定的几何图形。结合仅使用集成电路的一个或多个金属层中的导体的自动化位置和布线处理，可将备用栅极转换为有源栅极。

4. 发明授权

US06600341B2 Integrated circuit and associated design method using spare gate islands 有权
公开(公告)号：US06600341B2
公开(公告)日：2003-07-29
申请号：US10135325
申请日：2002-04-30
申请人： Craig Bingert , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
发明人： Craig Bingert , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
IPC分类号： H03K1900
CPC分类号： H01L27/11807
摘要： An integrated circuit includes standard cells interspersed with islands of spare gates. The spare gates are arranged in multiple groups of spare gates, with each group of spare gates within a corresponding designated spare gate area of a standard cell portion of the integrated circuit. At least a given one of the groups of spare gates is arranged between first and second rows of the standard cells and includes one or more rows of spare gates, with each row of spare gates including multiple base transistor structures arranged adjacent to one another along longitudinal dimensions of the structures. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool. The spare gates may be implemented using a base transistor structure compatible with the standard cell CAD tool. The spare gate islands may be distributed throughout the standard cell portion of the integrated circuit in a substantially uniform manner, for example, in accordance with a predetermined geometric pattern. The spare gates may be converted to active gates in conjunction with the automated place and route process using only conductors in one or more metal layers of the integrated circuit.

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