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1. 发明申请

US20070233856A1 Cross session process action 有权
标题翻译：跨会话过程动作
公开(公告)号：US20070233856A1
公开(公告)日：2007-10-04
申请号：US11396980
申请日：2006-04-03
申请人： Maxim Goldin , Richard Wurdack
发明人： Maxim Goldin , Richard Wurdack
IPC分类号： G06F15/173
CPC分类号： H04L67/14 , H04L67/146 , H04L67/148
摘要： Cross session process actions such as diagnostics in which a diagnostic process running in one process attaches and performs diagnostics on a process running in another session. Upon determining that diagnosis is to be performed on a process of another session, diagnostic process uses an intermediary session to launch diagnostic processes in the target session. Thus, actions such as diagnostics can be initiated across sessions.
摘要翻译：跨会话过程动作，例如诊断，其中在一个进程中运行的诊断进程在另一个会话中运行的进程上附加并执行诊断。在确定对另一会话的过程执行诊断时，诊断过程使用中间会话来在目标会话中启动诊断过程。因此，可以跨会话启动诸如诊断的动作。

2. 发明授权

US08473921B2 Debugging mechanisms in a cache-based memory isolation system 有权
标题翻译：基于缓存的内存隔离系统中的调试机制
公开(公告)号：US08473921B2
公开(公告)日：2013-06-25
申请号：US12646438
申请日：2009-12-23
申请人： Martin Taillefer , Ali-Reza Adl-Tabatabai , Gad Sheaffer , Peter Lachner , Richard Wurdack , Darek Mihocka , Jan Gray
发明人： Martin Taillefer , Ali-Reza Adl-Tabatabai , Gad Sheaffer , Peter Lachner , Richard Wurdack , Darek Mihocka , Jan Gray
IPC分类号： G06F9/44
CPC分类号： G06F11/362 , G06F12/0817
摘要： Debugging software in systems with architecturally significant processor caches. A method may be practiced in a computing environment. The method includes acts for debugging a software application, wherein the software application is configured to use one or more architecturally significant processor caches coupled to a processor. The method includes beginning execution of the software application. A debugger is run while executing the software application. The software application causes at least one of reads or writes to be made to the cache in an architecturally significant fashion. The reads or writes made to the cache in an architecturally significant fashion are preserved while performing debugging operations that would ordinarily disturb the reads or writes made to the cache in an architecturally significant fashion.
摘要翻译：在具有架构上重要的处理器高速缓存的系统中调试软件。可以在计算环境中实施一种方法。该方法包括用于调试软件应用程序的动作，其中软件应用被配置为使用耦合到处理器的一个或多个架构上重要的处理器高速缓存。该方法包括开始执行软件应用程序。在执行软件应用程序时运行调试器。软件应用程序使得以架构上显着的方式对缓存进行读取或写入中的至少一个。以架构上显着的方式对高速缓存进行的读取或写入被保留，同时执行调整操作，这些调试操作通常会以建筑上重要的方式干扰对高速缓存的读取或写入。

3. 发明申请

US20060212867A1 Determining an actual amount of time a processor consumes in executing a portion of code 有权
标题翻译：确定处理器在执行代码部分时消耗的实际时间
公开(公告)号：US20060212867A1
公开(公告)日：2006-09-21
申请号：US11082398
申请日：2005-03-17
申请人： Mahlon Fields , Richard Wurdack , Steven Carroll , Barry Nolte
发明人： Mahlon Fields , Richard Wurdack , Steven Carroll , Barry Nolte
IPC分类号： G06F9/46
CPC分类号： G06F11/3423
摘要： Systems and methods are provided that determine the actual amount of time a processor consumes in executing a code portion. The actual execution time of a code portion may be accurately determined by taking into consideration context switches and/or overhead time corresponding to the code portion. Determining the actual execution time of a code portion may include recording context switches and time values that occur during the execution of the code portion. This information along with overhead measurements may be used to generate the actual execution time of a code portion, as will be described in more detail below. For example, the switched-out intervals resulting from the context switches and the overhead time associated with the time measurements may be subtracted from the elapsed time to produce the actual execution time of a code portion.
摘要翻译：提供了确定处理器在执行代码部分时消耗的实际时间量的系统和方法。可以通过考虑与代码部分相对应的上下文切换和/或开销时间来精确地确定代码部分的实际执行时间。确定代码部分的实际执行时间可以包括在执行代码部分期间记录上下文切换和时间值。该信息以及开销测量可以用于生成代码部分的实际执行时间，如将在下面更详细描述的。例如，从上下文切换产生的切换间隔和与时间测量相关联的开销时间可以从经过的时间中减去以产生代码部分的实际执行时间。

4. 发明申请

US20110145498A1 INSTRUMENTATION OF HARDWARE ASSISTED TRANSACTIONAL MEMORY SYSTEM 有权
标题翻译：硬件辅助交易记录系统的仪器仪表
公开(公告)号：US20110145498A1
公开(公告)日：2011-06-16
申请号：US12638345
申请日：2009-12-15
申请人： Martin Taillefer , Jan Gray , Richard Wurdack , Gad Sheaffer , Ali-Reza Adl-Tabatabai
发明人： Martin Taillefer , Jan Gray , Richard Wurdack , Gad Sheaffer , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/08
CPC分类号： G06F9/467 , G06F11/3409 , G06F11/3466 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2201/86 , G06F2201/87 , G06F2201/88 , G06F2201/885
摘要： Monitoring performance of one or more architecturally significant processor caches coupled to a processor. The methods include executing an application on one or more processors coupled to one or more architecturally significant processor caches, where the application utilizes the architecturally significant portions of the architecturally significant processor caches. The methods further include at least one of generating metrics related to performance of the architecturally significant processor caches; implementing one or more debug exceptions related to performance of the architecturally significant processor caches; or implementing one or more transactional breakpoints related to performance of the architecturally significant processor caches as a result of utilizing the architecturally significant portions of the architecturally significant processor caches.
摘要翻译：监视耦合到处理器的一个或多个架构上重要的处理器高速缓存的性能。所述方法包括在耦合到一个或多个架构有意义的处理器高速缓存的一个或多个处理器上执行应用，其中应用利用架构上重要的处理器高速缓存的架构上重要的部分。所述方法还包括生成与架构上重要的处理器高速缓存的性能有关的度量中的至少一个; 实现与架构上重要的处理器高速缓存的性能相关的一个或多个调试异常; 或者通过利用架构上重要的处理器高速缓存的架构上重要的部分来实现与架构上重要的处理器高速缓存的性能相关的一个或多个事务性断点。

5. 发明授权

US09092253B2 Instrumentation of hardware assisted transactional memory system 有权
标题翻译：硬件辅助事务记忆体系统的设计
公开(公告)号：US09092253B2
公开(公告)日：2015-07-28
申请号：US12638345
申请日：2009-12-15
申请人： Martin Taillefer , Jan Gray , Richard Wurdack , Gad Sheaffer , Ali-Reza Adl Tabatabai
发明人： Martin Taillefer , Jan Gray , Richard Wurdack , Gad Sheaffer , Ali-Reza Adl Tabatabai
IPC分类号： G06F9/44 , G06F9/46 , G06F11/36 , G06F11/34
CPC分类号： G06F9/467 , G06F11/3409 , G06F11/3466 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2201/86 , G06F2201/87 , G06F2201/88 , G06F2201/885
摘要： Monitoring performance of one or more architecturally significant processor caches coupled to a processor. The methods include executing an application on one or more processors coupled to one or more architecturally significant processor caches, where the application utilizes the architecturally significant portions of the architecturally significant processor caches. The methods further include at least one of generating metrics related to performance of the architecturally significant processor caches; implementing one or more debug exceptions related to performance of the architecturally significant processor caches; or implementing one or more transactional breakpoints related to performance of the architecturally significant processor caches as a result of utilizing the architecturally significant portions of the architecturally significant processor caches.
摘要翻译：监视耦合到处理器的一个或多个架构上重要的处理器高速缓存的性能。所述方法包括在耦合到一个或多个架构有意义的处理器高速缓存的一个或多个处理器上执行应用，其中应用利用架构上重要的处理器高速缓存的架构上重要的部分。所述方法还包括生成与架构上重要的处理器高速缓存的性能有关的度量中的至少一个; 实现与架构上重要的处理器高速缓存的性能相关的一个或多个调试异常; 或者通过利用架构上重要的处理器高速缓存的架构上重要的部分来实现与架构上重要的处理器高速缓存的性能相关的一个或多个事务性断点。

6. 发明申请

US20110145798A1 DEBUGGING MECHANISMS IN A CACHE-BASED MEMORY ISOLATION SYSTEM 有权
标题翻译：基于缓存的内存分离系统中的调试机制
公开(公告)号：US20110145798A1
公开(公告)日：2011-06-16
申请号：US12646438
申请日：2009-12-23
申请人： Martin Taillefer , Ali-Reza Adl-Tabatabai , Gad Sheaffer , Peter Lachner , Richard Wurdack , Darek Mihocka , Jan Gray
发明人： Martin Taillefer , Ali-Reza Adl-Tabatabai , Gad Sheaffer , Peter Lachner , Richard Wurdack , Darek Mihocka , Jan Gray
IPC分类号： G06F9/44 , G06F15/76
CPC分类号： G06F11/362 , G06F12/0817
摘要： Debugging software in systems with architecturally significant processor caches. A method may be practiced in a computing environment. The method includes acts for debugging a software application, wherein the software application is configured to use one or more architecturally significant processor caches coupled to a processor. The method includes beginning execution of the software application. A debugger is run while executing the software application. The software application causes at least one of reads or writes to be made to the cache in an architecturally significant fashion. The reads or writes made to the cache in an architecturally significant fashion are preserved while performing debugging operations that would ordinarily disturb the reads or writes made to the cache in an architecturally significant fashion.
摘要翻译：在具有架构上重要的处理器高速缓存的系统中调试软件。可以在计算环境中实施一种方法。该方法包括用于调试软件应用程序的动作，其中软件应用被配置为使用耦合到处理器的一个或多个架构上重要的处理器高速缓存。该方法包括开始执行软件应用程序。在执行软件应用程序时运行调试器。软件应用程序使得以架构上显着的方式对缓存进行读取或写入中的至少一个。以架构上显着的方式对高速缓存进行的读取或写入被保留，同时执行调整操作，这些调试操作通常会以建筑上重要的方式干扰对高速缓存的读取或写入。

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