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1. 发明申请

US20120193715A1 STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS 审中-公开
标题翻译：结构与纳米尺度尺寸上的等温硅吸收型材
公开(公告)号：US20120193715A1
公开(公告)日：2012-08-02
申请号：US13442008
申请日：2012-04-09
申请人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
发明人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
IPC分类号： H01L29/772
CPC分类号： H01L29/7848 , H01L21/0237 , H01L21/02639 , H01L21/3065 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/78 , Y10S438/938
摘要： A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
摘要翻译：通过使用可以是栅极间隔物的掩模层的半导体材料层中的各向异性蚀刻形成沟槽。在一个实施例中，仅在包括沟槽的侧壁的半导体结构的垂直侧壁处在低温温度下提供吸附的氟层。一旦温度升高到低于低温的温度，吸附的氟层就可去除受控量的底层半导体材料。沟槽可以用另一种半导体材料填充以在半导体材料层中产生应力。在另一个实施例中，通过基于等离子体的蚀刻以受控的速率横向蚀刻半导体材料，而邻接的氧化物衬垫的水平部分防止半导体材料从沟槽的底表面蚀刻。

2. 发明申请

US20080191187A1 METHOD FOR MANUFACTURING A PHASE CHANGE MEMORY DEVICE WITH PILLAR BOTTOM ELECTRODE 有权
标题翻译：用于制造具有底部电极的相变存储器件的方法
公开(公告)号：US20080191187A1
公开(公告)日：2008-08-14
申请号：US11764678
申请日：2007-06-18
申请人： HSIANG LAN LUNG , CHIEH-FANG CHEN , YI-CHOU CHEN , SHIH HUNG CHEN , CHUNG HON LAM , ERIC ANDREW JOSEPH , ALEJANDRO GABRIEL SCHROTT , MATTHEW J. BREITWISCH , GEOFFREY WILLIAM BURR , THOMAS D. HAPP , JAN BORIS PHILIPP
发明人： HSIANG LAN LUNG , CHIEH-FANG CHEN , YI-CHOU CHEN , SHIH HUNG CHEN , CHUNG HON LAM , ERIC ANDREW JOSEPH , ALEJANDRO GABRIEL SCHROTT , MATTHEW J. BREITWISCH , GEOFFREY WILLIAM BURR , THOMAS D. HAPP , JAN BORIS PHILIPP
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/14 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of conductive contacts. Electrode material is etched to form a pattern of electrode pillars on corresponding conductive contacts. Next, a dielectric material is deposited over the pattern and planarized to provide an electrode surface exposing top surfaces of the electrode pillars. Next, a layer of programmable resistive material, such as a chalcogenide or other phase change material, is deposited, followed by deposition of a layer of a top electrode material. A device including bottom electrode pillars with larger bottom surfaces than top surfaces is described.
摘要翻译：用于制造蘑菇细胞型相变存储器的方法是基于在包括与接入电路电连通的导电触点阵列的基板上制造底部电极材料的柱。沉积一层电极材料，使其与导电触点阵列可靠地电接触。蚀刻电极材料以在对应的导电触点上形成电极柱的图案。接下来，将介电材料沉积在图案上并且被平坦化以提供暴露电极柱顶表面的电极表面。接下来，沉积诸如硫族化物或其它相变材料的可编程电阻材料层，随后沉积顶层电极材料层。描述了包括具有比顶表面更大的底表面的底部电极柱的装置。

3. 发明申请

US20080164452A1 Scaled-Down Phase Change Memory Cell in Recessed Heater 有权
标题翻译：嵌入式加热器中的缩小相变存储单元
公开(公告)号：US20080164452A1
公开(公告)日：2008-07-10
申请号：US11620138
申请日：2007-01-05
申请人： Eric Andrew Joseph , Chung Hon Lam , Alejandro Gabriel Schrott
发明人： Eric Andrew Joseph , Chung Hon Lam , Alejandro Gabriel Schrott
IPC分类号： H01L45/00
CPC分类号： H01L45/1233 , H01L27/2436 , H01L45/06 , H01L45/1246 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1691
摘要： A semiconductor structure configurable for use as a nonvolatile storage element includes a first electrode, an insulating layer formed on at least a portion of an upper surface of the first electrode, and a pillar traversing the insulating layer and being recessed relative to an upper surface of the insulating layer. The pillar includes a heater formed on at least a portion of the upper surface of the first electrode and a collar formed on sidewalls of the insulating layer proximate the heater and on at least a portion of an upper surface of the heater. The structure further includes a PCM layer formed on at least a portion of the upper surface of the insulating layer and substantially filling a volume defined by the upper surface of the heater and at least a portion of an upper surface of the collar. A second electrode is formed on at least a portion of an upper surface of the phase change material layer.
摘要翻译：可配置为用作非易失性存储元件的半导体结构包括第一电极，形成在第一电极的上表面的至少一部分上的绝缘层和穿过绝缘层并且相对于第一电极的上表面凹陷的柱绝缘层。支柱包括形成在第一电极的上表面的至少一部分上的加热器和形成在靠近加热器的绝缘层的侧壁上和在加热器的上表面的至少一部分上的套环。该结构还包括形成在绝缘层的上表面的至少一部分上并基本上填充由加热器的上表面限定的体积和套环的上表面的至少一部分的PCM层。第二电极形成在相变材料层的上表面的至少一部分上。

4. 发明申请

US20120193680A1 STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS 审中-公开
公开(公告)号：US20120193680A1
公开(公告)日：2012-08-02
申请号：US13442011
申请日：2012-04-09
申请人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
发明人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
IPC分类号： H01L29/78 , H01L21/306 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/0237 , H01L21/02639 , H01L21/3065 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/78 , Y10S438/938
摘要： A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

5. 发明授权

US08232171B2 Structure with isotropic silicon recess profile in nanoscale dimensions 有权
标题翻译：具有纳米级尺寸的各向同性硅凹槽轮廓的结构
公开(公告)号：US08232171B2
公开(公告)日：2012-07-31
申请号：US12561704
申请日：2009-09-17
申请人： Sebastian Ulrich Engelmann , Nicholas C. M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
发明人： Sebastian Ulrich Engelmann , Nicholas C. M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/0237 , H01L21/02639 , H01L21/3065 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/78 , Y10S438/938
摘要： A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
摘要翻译：通过使用可以是栅极间隔物的掩模层的半导体材料层中的各向异性蚀刻形成沟槽。在一个实施例中，仅在包括沟槽的侧壁的半导体结构的垂直侧壁处在低温温度下提供吸附的氟层。一旦温度升高到低于低温的温度，吸附的氟层就可去除受控量的底层半导体材料。沟槽可以用另一种半导体材料填充以在半导体材料层中产生应力。在另一个实施例中，通过基于等离子体的蚀刻以受控的速率横向蚀刻半导体材料，而邻接氧化物衬垫的水平部分防止半导体材料从沟槽的底表面蚀刻。

6. 发明申请

US20090294748A1 Phase Change Memory Cell with Reduced Switchable Volume 有权
标题翻译：具有可切换容积的相变存储器单元
公开(公告)号：US20090294748A1
公开(公告)日：2009-12-03
申请号：US12498840
申请日：2009-07-07
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric Andrew Joseph , Chung Hon Lam , Hsiang-Lan Lung , Alejandro Gabriel Schrott
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric Andrew Joseph , Chung Hon Lam , Hsiang-Lan Lung , Alejandro Gabriel Schrott
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1666
摘要： A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.
摘要翻译：通过形成电介质层并在电介质层中构图孔来制造存储单元。至少部分地通过在有效去除与催化材料接触的电介质层的那些区域的条件下在反应物存在下使介电层与催化材料接触来对孔进行图案化。然后形成与电介质层接触的相变特征，使得相变特征的一部分至少部分地填充介电层中的孔。图案化介电层的至少一部分保留在最终存储单元中。

7. 发明授权

US08426967B2 Scaled-down phase change memory cell in recessed heater 有权
标题翻译：嵌入式加热器中的缩小相变存储单元
公开(公告)号：US08426967B2
公开(公告)日：2013-04-23
申请号：US11620138
申请日：2007-01-05
申请人： Eric Andrew Joseph , Chung Hon Lam , Alejandro Gabriel Schrott
发明人： Eric Andrew Joseph , Chung Hon Lam , Alejandro Gabriel Schrott
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/06
CPC分类号： H01L45/1233 , H01L27/2436 , H01L45/06 , H01L45/1246 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1691
摘要： A semiconductor structure configurable for use as a nonvolatile storage element includes a first electrode, an insulating layer formed on at least a portion of an upper surface of the first electrode, and a pillar traversing the insulating layer and being recessed relative to an upper surface of the insulating layer. The pillar includes a heater formed on at least a portion of the upper surface of the first electrode and a collar formed on sidewalls of the insulating layer proximate the heater and on at least a portion of an upper surface of the heater. The structure further includes a PCM layer formed on at least a portion of the upper surface of the insulating layer and substantially filling a volume defined by the upper surface of the heater and at least a portion of an upper surface of the collar. A second electrode is formed on at least a portion of an upper surface of the phase change material layer.
摘要翻译：可配置为用作非易失性存储元件的半导体结构包括第一电极，形成在第一电极的上表面的至少一部分上的绝缘层和穿过绝缘层并且相对于第一电极的上表面凹陷的柱绝缘层。支柱包括形成在第一电极的上表面的至少一部分上的加热器和形成在靠近加热器的绝缘层的侧壁上和在加热器的上表面的至少一部分上的套环。该结构还包括形成在绝缘层的上表面的至少一部分上并基本上填充由加热器的上表面限定的体积和套环的上表面的至少一部分的PCM层。第二电极形成在相变材料层的上表面的至少一部分上。

8. 发明授权

US08138028B2 Method for manufacturing a phase change memory device with pillar bottom electrode 有权
标题翻译：具有柱底电极的相变存储器件的制造方法
公开(公告)号：US08138028B2
公开(公告)日：2012-03-20
申请号：US11764678
申请日：2007-06-18
申请人： Hsiang Lan Lung , Chieh Fang Chen , Yi Chou Chen , Shih Hung Chen , Chung Hon Lam , Eric Andrew Joseph , Alejandro Gabriel Schrott , Matthew J. Breitwisch , Geoffrey William Burr , Thomas D. Happ , Jan Boris Philipp
发明人： Hsiang Lan Lung , Chieh Fang Chen , Yi Chou Chen , Shih Hung Chen , Chung Hon Lam , Eric Andrew Joseph , Alejandro Gabriel Schrott , Matthew J. Breitwisch , Geoffrey William Burr , Thomas D. Happ , Jan Boris Philipp
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/14 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of conductive contacts. Electrode material is etched to form a pattern of electrode pillars on corresponding conductive contacts. Next, a dielectric material is deposited over the pattern and planarized to provide an electrode surface exposing top surfaces of the electrode pillars. Next, a layer of programmable resistive material, such as a chalcogenide or other phase change material, is deposited, followed by deposition of a layer of a top electrode material. A device including bottom electrode pillars with larger bottom surfaces than top surfaces is described.
摘要翻译：用于制造蘑菇细胞型相变存储器的方法是基于在包括与接入电路电连通的导电触点阵列的基板上制造底部电极材料的柱。沉积一层电极材料，使其与导电触点阵列可靠地电接触。蚀刻电极材料以在对应的导电触点上形成电极柱的图案。接下来，将介电材料沉积在图案上并且被平坦化以提供暴露电极柱顶表面的电极表面。接下来，沉积诸如硫族化物或其它相变材料的可编程电阻材料层，随后沉积顶层电极材料层。描述了包括具有比顶表面更大的底表面的底部电极柱的装置。

9. 发明授权

US08115186B2 Phase change memory cell with reduced switchable volume 有权
标题翻译：相变容量小的相变存储单元
公开(公告)号：US08115186B2
公开(公告)日：2012-02-14
申请号：US12498840
申请日：2009-07-07
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric Andrew Joseph , Chung Hon Lam , Hsiang-Lan Lung , Alejandro Gabriel Schrott
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric Andrew Joseph , Chung Hon Lam , Hsiang-Lan Lung , Alejandro Gabriel Schrott
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： H01L45/144 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1666
摘要： A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.
摘要翻译：通过形成电介质层并在电介质层中构图孔来制造存储单元。至少部分地通过在有效去除与催化材料接触的电介质层的那些区域的条件下在反应物存在下使介电层与催化材料接触来对孔进行图案化。然后形成与电介质层接触的相变特征，使得相变特征的一部分至少部分地填充介电层中的孔。图案化介电层的至少一部分保留在最终存储单元中。

10. 发明申请

US20110062494A1 STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS 有权
标题翻译：结构与纳米尺度尺寸上的等温硅吸收型材
公开(公告)号：US20110062494A1
公开(公告)日：2011-03-17
申请号：US12561704
申请日：2009-09-17
申请人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
发明人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
IPC分类号： H01L29/78 , H01L21/20 , H01L29/06 , H01L21/302
CPC分类号： H01L29/7848 , H01L21/0237 , H01L21/02639 , H01L21/3065 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/78 , Y10S438/938
摘要： A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
摘要翻译：通过使用可以是栅极间隔物的掩模层的半导体材料层中的各向异性蚀刻形成沟槽。在一个实施例中，仅在包括沟槽的侧壁的半导体结构的垂直侧壁处在低温温度下提供吸附的氟层。一旦温度升高到低于低温的温度，吸附的氟层就可去除受控量的底层半导体材料。沟槽可以用另一种半导体材料填充以在半导体材料层中产生应力。在另一个实施例中，通过基于等离子体的蚀刻以受控的速率横向蚀刻半导体材料，而邻接氧化物衬垫的水平部分防止半导体材料从沟槽的底表面蚀刻。

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