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1. 发明申请

US20120187536A1 COMPLIMENTARY METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHOD OF MANUFACTURE 有权
标题翻译：合金金属绝缘子金属（MIM）电容器及其制造方法
公开(公告)号：US20120187536A1
公开(公告)日：2012-07-26
申请号：US13427216
申请日：2012-03-22
申请人： James S. DUNN , Zhong - Xiang HE , Anthony K. STAMPER
发明人： James S. DUNN , Zhong - Xiang HE , Anthony K. STAMPER
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01G4/33 , H01G4/1209 , H01G4/232 , H01G4/38 , H01L23/5223 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , Y10T29/43 , Y10T29/435 , Y10T29/49156 , H01L2924/00
摘要： A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.
摘要翻译：同时形成在单个晶片上的高密度电容器和低密度电容器和制造方法。该方法包括在电介质材料上沉积底板; 在底板上沉积低k介质; 在低k电介质和底板上沉积高k电介质; 在高k电介质上沉积顶板; 以及蚀刻所述底板和所述高k电介质的一部分以形成具有第一厚度的电介质堆叠的第一金属 - 绝缘体金属（MIM）电容器和具有不同于第二厚度的第二厚度的电介质叠层的第二MIM电容器第一厚度。

2. 发明授权

US07303968B2 Semiconductor device and method having multiple subcollectors formed on a common wafer 有权
标题翻译：具有形成在公共晶片上的多个子集电极的半导体器件和方法
公开(公告)号：US07303968B2
公开(公告)日：2007-12-04
申请号：US11299682
申请日：2005-12-13
申请人： James S. Dunn , Louis D. Lanzerotti , Steven H. Voldman
发明人： James S. Dunn , Louis D. Lanzerotti , Steven H. Voldman
IPC分类号： H01L21/8222 , H01L21/331 , H01L21/8249
CPC分类号： H01L27/0623 , H01L21/8249 , H01L29/0821
摘要： A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.
摘要翻译：提供半导体器件和制造具有形成在公共晶片中的多个子集电极的半导体器件的方法，以提供具有不同特性和频率响应的多个结构。子集电极可以使用不同剂量或不同的材料注入来提供，导致具有不同最佳单位电流增益截止频率（击穿电压）和击穿电压（BV＆lt; SUB> CBO ）。

3. 发明授权

US07265018B2 Method to build self-aligned NPN in advanced BiCMOS technology 有权
标题翻译：在先进的BiCMOS技术中构建自对准NPN的方法
公开(公告)号：US07265018B2
公开(公告)日：2007-09-04
申请号：US10711486
申请日：2004-09-21
申请人： James S. Dunn , Alvin J. Joseph , Qizhi Liu
发明人： James S. Dunn , Alvin J. Joseph , Qizhi Liu
IPC分类号： H01L21/8222
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single crystal silicon and polycrystalline silicon is different and by using a low temperature oxidation process such as a high-pressure oxidation (HIPOX) process to form a self-aligned emitter/extrinsic base HBT structure.
摘要翻译：本发明提供了一种在BiCMOS技术中形成自对准异双极晶体管（HBT）器件的方法。该方法包括通过使用其中单晶硅和多晶硅的生长速率不同的外延生长工艺和通过使用诸如高压氧化（HIPOX）工艺的低温氧化工艺形成凸起的外在基体结构来形成自对准发射极/非本征基极HBT结构。

4. 发明授权

US07064416B2 Semiconductor device and method having multiple subcollectors formed on a common wafer 失效
标题翻译：具有形成在公共晶片上的多个子集电极的半导体器件和方法
公开(公告)号：US07064416B2
公开(公告)日：2006-06-20
申请号：US09991142
申请日：2001-11-16
申请人： James S. Dunn , Louis D. Lanzerotti , Steven H. Voldman
发明人： James S. Dunn , Louis D. Lanzerotti , Steven H. Voldman
IPC分类号： H01L27/082
CPC分类号： H01L27/0623 , H01L21/8249 , H01L29/0821
摘要： A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.
摘要翻译：提供半导体器件和制造具有形成在公共晶片中的多个子集电极的半导体器件的方法，以提供具有不同特性和频率响应的多个结构。子集电极可以使用不同剂量或不同的材料注入来提供，导致具有不同最佳单位电流增益截止频率（击穿电压）和击穿电压（BV＆lt; SUB> CBO ）。

5. 发明授权

US06891251B2 Varactors for CMOS and BiCMOS technologies 有权
标题翻译： CMOS和BiCMOS技术的变容二极管
公开(公告)号：US06891251B2
公开(公告)日：2005-05-10
申请号：US10323022
申请日：2002-12-18
申请人： Douglas D. Coolbaugh , James S. Dunn , Michael D. Gordon , Mohammed Y. Hammad , Jeffrey B. Johnson , David C. Sheridan
发明人： Douglas D. Coolbaugh , James S. Dunn , Michael D. Gordon , Mohammed Y. Hammad , Jeffrey B. Johnson , David C. Sheridan
IPC分类号： H01L21/8222 , H01L27/08 , H01L29/93 , H01L29/94
CPC分类号： H01L27/0811 , H01L27/0808 , H01L29/93 , H01L29/94
摘要： Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.
摘要翻译：提供了具有高可调性和/或与之相关的高品质因素的变形反应器及其制造方法。公开的一种类型的变容二极管是准超突发的基极 - 集电极结变容二极管，其包括在子集电极区域顶部具有第一导电类型的集电极区域的基板，所述集电极区域中存在多个隔离区域; 位于至少一对隔离区之间的贯穿植入区; 所述SiGe层位于所述衬底的不包含直通注入区域的部分之上，所述SiGe层具有不同于所述第一导电类型的第二导电类型的非本征基区; 以及位于外部基极区域和子集电极区域之间的锑注入区域。所公开的另一种类型的变容二极管是MOS变容二极管，其至少包括多晶硅栅极区域和阱区域，其中多晶硅栅极区域和阱区域具有相反的极性。

6. 发明授权

US06683345B1 Semiconductor device and method for making the device having an electrically modulated conduction channel 有权
标题翻译：用于制造具有电调制传导通道的器件的半导体器件和方法
公开(公告)号：US06683345B1
公开(公告)日：2004-01-27
申请号：US09467537
申请日：1999-12-20
申请人： Eric Adler , James S. Dunn , Joseph Iadanza , Jenifer E. Lary , Kent E. Morrett , Josef S. Watts
发明人： Eric Adler , James S. Dunn , Joseph Iadanza , Jenifer E. Lary , Kent E. Morrett , Josef S. Watts
IPC分类号： H01L2976
CPC分类号： H01L29/8605 , H01L21/823412 , H01L21/823481 , H01L27/0802 , H01L29/78 , H03M1/0604 , H03M1/66
摘要： A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaining portion of the substrate. The trench walls are made thin enough so that the width of the channel within a diffusion region may be controlled by applying an electrical potential between a trench wall and the substrate. Transistors formed within the trench structure have a conduction channel width controlled by the applied voltage permitting the gain of the transistor to be matched with the gain of other transistors on the substrate.
摘要翻译：具有电调制的导电通道的半导体器件。在包围扩散区域的衬底内形成沟槽结构。沟槽结构将形成在扩散区域内的器件与衬底的剩余部分隔离。沟壁被制成足够薄，使得扩散区域内的通道的宽度可以通过在沟槽壁和衬底之间施加电势来控制。形成在沟槽结构内的晶体管具有由所施加的电压控制的导通沟道宽度，允许晶体管的增益与衬底上的其它晶体管的增益匹配。

7. 发明授权

US06521506B1 Varactors for CMOS and BiCMOS technologies 失效
标题翻译： CMOS和BiCMOS技术的变容二极管
公开(公告)号：US06521506B1
公开(公告)日：2003-02-18
申请号：US10016539
申请日：2001-12-13
申请人： Douglas D. Coolbaugh , James S. Dunn , Michael D. Gordon , Mohamed Y. Hammad , Jeffrey B. Johnson , David C. Sheridan
发明人： Douglas D. Coolbaugh , James S. Dunn , Michael D. Gordon , Mohamed Y. Hammad , Jeffrey B. Johnson , David C. Sheridan
IPC分类号： H01L2120
CPC分类号： H01L27/0811 , H01L27/0808 , H01L29/93 , H01L29/94
摘要： Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.
摘要翻译：提供了具有高可调性和/或与之相关的高品质因素的变形反应器及其制造方法。公开的一种类型的变容二极管是准超突发的基极 - 集电极结变容二极管，其包括在子集电极区域顶部具有第一导电类型的集电极区域的基板，所述集电极区域中存在多个隔离区域; 位于至少一对隔离区之间的贯穿植入区; 所述SiGe层位于所述衬底的不包含直通注入区域的部分之上，所述SiGe层具有不同于所述第一导电类型的第二导电类型的非本征基区; 以及位于外部基极区域和子集电极区域之间的锑注入区域。所公开的另一种类型的变容二极管是MOS变容二极管，其至少包括多晶硅栅极区域和阱区域，其中多晶硅栅极区域和阱区域具有相反的极性。

8. 发明授权

US06448124B1 Method for epitaxial bipolar BiCMOS 失效
标题翻译：外延双极BiCMOS的方法
公开(公告)号：US06448124B1
公开(公告)日：2002-09-10
申请号：US09439067
申请日：1999-11-12
申请人： Douglas D. Coolbaugh , James S. Dunn , Peter J. Geiss , Peter B. Gray , David L. Harame , Kathryn T. Schonenberg , Stephen A. St. Onge , Seshadri Subbanna
发明人： Douglas D. Coolbaugh , James S. Dunn , Peter J. Geiss , Peter B. Gray , David L. Harame , Kathryn T. Schonenberg , Stephen A. St. Onge , Seshadri Subbanna
IPC分类号： H01L218238
CPC分类号： H01L21/76224 , H01L21/763 , H01L21/8249
摘要： A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.
摘要翻译：提供一种形成BiCMOS集成电路的方法，其包括以下步骤：（a）在衬底的第一区域中形成双极器件的第一部分; （b）在所述第一区域上形成第一保护层以保护所述双极器件的所述第一部分; （c）在所述衬底的第二区域中形成场效应晶体管器件; （d）在所述衬底的所述第二区域上形成第二保护层以保护所述场效应晶体管器件; （e）去除所述第一保护层; （f）在所述衬底的所述第一区域中形成所述双极器件的第二部分; 和（g）去除所述第二保护层。

9. 发明授权

US06255178B1 Method for forming transistors with raised source and drains and device formed thereby 有权
标题翻译：用于形成具有升高的源极和漏极的晶体管的方法以及由此形成的器件
公开(公告)号：US06255178B1
公开(公告)日：2001-07-03
申请号：US09368767
申请日：1999-08-05
申请人： Jeffrey S. Brown , James S. Dunn , Steven J. Holmes , David V. Horak , Robert K. Leidy , Steven H. Voldman
发明人： Jeffrey S. Brown , James S. Dunn , Steven J. Holmes , David V. Horak , Robert K. Leidy , Steven H. Voldman
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , G03F7/095 , G03F7/38 , H01L21/0274 , H01L21/26586 , H01L21/31116 , H01L21/31144 , H01L29/6659
摘要： The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.
摘要翻译：本发明的优选实施例提供了克服现有技术的缺点的晶体管结构及其制造方法。特别地，优选的结构和方法通过使用通过电介质层与衬底部分隔离的凸起源极和漏极导致较低的漏电和结电容。升高的源极和漏极优选由用于形成晶体管栅极的相同材料层制成。用于制造晶体管的优选方法使用混合抗蚀剂将栅极材料层精确地图案化成用于栅极，源极和漏极的区域。然后通过生长硅将源极区和漏极区连接到衬底。因此，优选的方法导致改进的晶体管结构，而不需要过多的制造步骤。

10. 发明授权

US6100013A Method for forming transistors with raised source and drains and device formed thereby 失效
标题翻译：用于形成具有升高的源极和漏极的晶体管的方法以及由此形成的器件
公开(公告)号：US6100013A
公开(公告)日：2000-08-08
申请号：US71207
申请日：1998-05-01
申请人： Jeffery S. Brown , James S. Dunn , Steven J. Holmes , David V. Horak , Robert K. Leidy , Steven H. Voldman
发明人： Jeffery S. Brown , James S. Dunn , Steven J. Holmes , David V. Horak , Robert K. Leidy , Steven H. Voldman
IPC分类号： H01L29/78 , G03F7/095 , G03F7/38 , H01L21/027 , H01L21/265 , H01L21/311 , H01L21/336 , G03F7/20
CPC分类号： H01L29/66492 , G03F7/38 , H01L21/0274 , H01L21/31116 , H01L21/31144 , H01L29/6659 , G03F7/095 , H01L21/26586
摘要： The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.
摘要翻译：本发明的优选实施例提供了克服现有技术的缺点的晶体管结构及其制造方法。特别地，优选的结构和方法通过使用通过电介质层与衬底部分隔离的凸起源极和漏极导致较低的漏电和结电容。升高的源极和漏极优选由用于形成晶体管栅极的相同材料层制成。用于制造晶体管的优选方法使用混合抗蚀剂将栅极材料层精确地图案化成用于栅极，源极和漏极的区域。然后通过生长硅将源极区和漏极区连接到衬底。因此，优选的方法导致改进的晶体管结构，而不需要过多的制造步骤。

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