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1. 发明授权

US06255178B1 Method for forming transistors with raised source and drains and device formed thereby 有权
标题翻译：用于形成具有升高的源极和漏极的晶体管的方法以及由此形成的器件
公开(公告)号：US06255178B1
公开(公告)日：2001-07-03
申请号：US09368767
申请日：1999-08-05
申请人： Jeffrey S. Brown , James S. Dunn , Steven J. Holmes , David V. Horak , Robert K. Leidy , Steven H. Voldman
发明人： Jeffrey S. Brown , James S. Dunn , Steven J. Holmes , David V. Horak , Robert K. Leidy , Steven H. Voldman
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , G03F7/095 , G03F7/38 , H01L21/0274 , H01L21/26586 , H01L21/31116 , H01L21/31144 , H01L29/6659
摘要： The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.
摘要翻译：本发明的优选实施例提供了克服现有技术的缺点的晶体管结构及其制造方法。特别地，优选的结构和方法通过使用通过电介质层与衬底部分隔离的凸起源极和漏极导致较低的漏电和结电容。升高的源极和漏极优选由用于形成晶体管栅极的相同材料层制成。用于制造晶体管的优选方法使用混合抗蚀剂将栅极材料层精确地图案化成用于栅极，源极和漏极的区域。然后通过生长硅将源极区和漏极区连接到衬底。因此，优选的方法导致改进的晶体管结构，而不需要过多的制造步骤。

2. 发明授权

US06420766B1 Transistor having raised source and drain 有权
标题翻译：晶体管升高源极和漏极
公开(公告)号：US06420766B1
公开(公告)日：2002-07-16
申请号：US09368843
申请日：1999-08-05
申请人： Jeffrey S. Brown , James S. Dunn , Steven J. Holmes , David V. Horak , Robert K. Leidy , Steven H. Voldman
发明人： Jeffrey S. Brown , James S. Dunn , Steven J. Holmes , David V. Horak , Robert K. Leidy , Steven H. Voldman
IPC分类号： H01L2976
CPC分类号： H01L29/66492 , G03F7/095 , G03F7/38 , H01L21/0274 , H01L21/26586 , H01L21/31116 , H01L21/31144 , H01L29/6659
摘要： The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.
摘要翻译：本发明的优选实施例提供了克服现有技术的缺点的晶体管结构及其制造方法。特别地，优选的结构和方法通过使用通过电介质层与衬底部分隔离的凸起源极和漏极导致较低的漏电和结电容。升高的源极和漏极优选由用于形成晶体管栅极的相同材料层制成。用于制造晶体管的优选方法使用混合抗蚀剂将栅极材料层精确地图案化成用于栅极，源极和漏极的区域。然后通过生长硅将源极区和漏极区连接到衬底。因此，优选的方法导致改进的晶体管结构，而不需要过多的制造步骤。

3. 发明授权

US6100013A Method for forming transistors with raised source and drains and device formed thereby 失效
标题翻译：用于形成具有升高的源极和漏极的晶体管的方法以及由此形成的器件
公开(公告)号：US6100013A
公开(公告)日：2000-08-08
申请号：US71207
申请日：1998-05-01
申请人： Jeffery S. Brown , James S. Dunn , Steven J. Holmes , David V. Horak , Robert K. Leidy , Steven H. Voldman
发明人： Jeffery S. Brown , James S. Dunn , Steven J. Holmes , David V. Horak , Robert K. Leidy , Steven H. Voldman
IPC分类号： H01L29/78 , G03F7/095 , G03F7/38 , H01L21/027 , H01L21/265 , H01L21/311 , H01L21/336 , G03F7/20
CPC分类号： H01L29/66492 , G03F7/38 , H01L21/0274 , H01L21/31116 , H01L21/31144 , H01L29/6659 , G03F7/095 , H01L21/26586
摘要： The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.
摘要翻译：本发明的优选实施例提供了克服现有技术的缺点的晶体管结构及其制造方法。特别地，优选的结构和方法通过使用通过电介质层与衬底部分隔离的凸起源极和漏极导致较低的漏电和结电容。升高的源极和漏极优选由用于形成晶体管栅极的相同材料层制成。用于制造晶体管的优选方法使用混合抗蚀剂将栅极材料层精确地图案化成用于栅极，源极和漏极的区域。然后通过生长硅将源极区和漏极区连接到衬底。因此，优选的方法导致改进的晶体管结构，而不需要过多的制造步骤。

4. 发明授权

US5939767A Structure and process for buried diode formation in CMOS 失效
标题翻译： CMOS中埋地二极管形成的结构和工艺
公开(公告)号：US5939767A
公开(公告)日：1999-08-17
申请号：US052512
申请日：1998-03-31
申请人： Jeffrey S. Brown , Steven J. Holmes , Robert K. Leidy , Steven H. Voldman
发明人： Jeffrey S. Brown , Steven J. Holmes , Robert K. Leidy , Steven H. Voldman
IPC分类号： H01L21/8238 , H01L27/02 , H01L27/092 , H01L29/866 , H01L29/00 , H01L29/861 , H01L31/107
CPC分类号： H01L27/0255 , H01L21/8238
摘要： According to the present invention, an improved method for buried diode formation in CMOS processing is disclosed. Using a hybrid photoresist process, a self-aligning Zener diode is created using a two-step photolithography mask process. Since the process disclosed in the invention uses only the p-well and the n-well masks to create the Zener diode, photolithography alignment problems are reduced and Zener diodes can be create at the sub-micron scale.
摘要翻译：根据本发明，公开了一种用于CMOS处理中的埋二极管形成的改进方法。使用混合光刻胶工艺，使用两步光刻掩模工艺创建自对准齐纳二极管。由于本发明公开的方法仅使用p阱和n-阱掩模来产生齐纳二极管，所以减小了光刻对准问题，并且可以在亚微米级产生齐纳二极管。

5. 发明授权

US06232639B1 Method and structure to reduce latch-up using edge implants 失效
标题翻译：使用边缘植入物减少闭锁的方法和结构
公开(公告)号：US06232639B1
公开(公告)日：2001-05-15
申请号：US09107900
申请日：1998-06-30
申请人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
发明人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
IPC分类号： H01L2976
CPC分类号： H01L21/823878 , H01L27/0921 , Y10S148/137
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.
摘要翻译：本发明的优选实施例克服了现有技术的限制，并且提供了一种通过在阱边缘处形成植入物来增加CMOS器件的闩锁抗扰度的装置和方法。优选的方法使用混合抗蚀剂在N阱和/或P阱的边缘形成这些植入物。植入物减少了寄生晶体管中少数载流子的寿命，从而降低了寄生晶体管的增益。这降低了CMOS器件闭锁的倾向。优选实施例方法允许形成这些植入物，而不需要比现有技术方法更多的掩蔽步骤。此外，用于形成植入物的优选方法导致与孔的边缘自对准的植入物。

6. 发明授权

US6033949A Method and structure to reduce latch-up using edge implants 失效
标题翻译：使用边缘植入物减少闭锁的方法和结构
公开(公告)号：US6033949A
公开(公告)日：2000-03-07
申请号：US107813
申请日：1998-06-30
申请人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
发明人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
IPC分类号： H01L21/761 , G03F7/004 , H01L21/8238 , H01L27/08 , H01L27/092
CPC分类号： H01L21/823878 , H01L27/0921 , Y10S148/137
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.
摘要翻译：本发明的优选实施例克服了现有技术的限制，并且提供了一种通过在阱边缘处形成植入物来增加CMOS器件的闩锁抗扰度的装置和方法。优选的方法使用混合抗蚀剂在N阱和/或P阱的边缘形成这些植入物。植入物减少了寄生晶体管中少数载流子的寿命，从而降低了寄生晶体管的增益。这降低了CMOS器件闭锁的倾向。优选实施例方法允许形成这些植入物，而不需要比现有技术方法更多的掩蔽步骤。此外，用于形成植入物的优选方法导致与孔的边缘自对准的植入物。

7. 发明授权

US5882967A Process for buried diode formation in CMOS 失效
标题翻译： CMOS中埋入二极管形成工艺
公开(公告)号：US5882967A
公开(公告)日：1999-03-16
申请号：US852850
申请日：1997-05-07
申请人： Jeffrey S. Brown , Steven J. Holmes , Robert K. Leidy , Steven H. Voldman
发明人： Jeffrey S. Brown , Steven J. Holmes , Robert K. Leidy , Steven H. Voldman
IPC分类号： H01L21/8238 , H01L27/02 , H01L27/092 , H01L29/866 , H01L21/8234
CPC分类号： H01L27/0255 , H01L21/8238
摘要： According to the present invention, an improved method for buried diode formation in CMOS processing is disclosed. Using a hybrid photoresist process, a self-aligning Zener diode is created using a two-step photolithography mask process. Since the process disclosed in the invention uses only the p-well and the n-well masks to create the Zener diode, photolithography alignment problems are reduced and Zener diodes can be create at the sub-micron scale.
摘要翻译：根据本发明，公开了一种用于CMOS处理中的埋二极管形成的改进方法。使用混合光刻胶工艺，使用两步光刻掩模工艺创建自对准齐纳二极管。由于本发明公开的方法仅使用p阱和n-阱掩模来产生齐纳二极管，所以减小了光刻对准问题，并且可以在亚微米级产生齐纳二极管。

8. 发明授权

US06218704B1 ESD protection structure and method 失效
标题翻译：具有沟槽隔离结构下植入物的ESD保护结构
公开(公告)号：US06218704B1
公开(公告)日：2001-04-17
申请号：US08851973
申请日：1997-05-07
申请人： Jeffrey S. Brown , Steven J. Holmes , Robert K. Leidy , Steven H. Voldman
发明人： Jeffrey S. Brown , Steven J. Holmes , Robert K. Leidy , Steven H. Voldman
IPC分类号： H01L2362
CPC分类号： H01L27/0288 , H01L27/0255 , H01L29/1083 , H01L2924/0002 , H01L2924/00
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the robustness of electrostatic discharge (ESD) protection devices by reducing the temperature gradient caused by ESD pulses and reducing the likelihood of thermal runaway caused by large ESD pulses. The preferred embodiment forms implants under the trench isolation structures in the ESD devices. The implants reduce the current-caused heating that can lead to thermal runaway, and thus improve the robustness of the ESD protection device. In the preferred embodiment, the implants are formed using hybrid resist. The hybrid resist provides a method to form that implants that does not require additional masking steps or other excessive processing. Additionally, the hybrid resist provides implants that are self aligned with the well regions.
摘要翻译：本发明的优选实施例克服了现有技术的限制，并且提供了一种通过降低ESD脉冲引起的温度梯度并降低由于静电放电（ESD）保护装置引起的热失控的可能性而增加静电放电（ESD）保护装置的鲁棒性的装置和方法大ESD脉冲。优选实施例在ESD器件中的沟槽隔离结构之下形成植入物。植入物减少导致热失控的电流引起的加热，从而提高ESD保护装置的鲁棒性。在优选实施例中，使用混合抗蚀剂形成植入物。混合抗蚀剂提供了形成不需要额外掩蔽步骤或其它过量处理的植入物的方法。此外，混合抗蚀剂提供与阱区自对准的植入物。

9. 发明授权

US5861330A Method and structure to reduce latch-up using edge implants 失效
公开(公告)号：US5861330A
公开(公告)日：1999-01-19
申请号：US852466
申请日：1997-05-07
申请人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
发明人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
IPC分类号： H01L21/761 , G03F7/004 , H01L21/8238 , H01L27/08 , H01L27/092
CPC分类号： H01L21/823878 , H01L27/0921 , Y10S148/137
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

10. 发明授权

US5976768A Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby 失效
标题翻译：使用倍频混合抗蚀剂和由此形成的器件形成侧壁间隔物的方法
公开(公告)号：US5976768A
公开(公告)日：1999-11-02
申请号：US140593
申请日：1998-08-26
申请人： Jeffrey S. Brown , James S. Dunn , Steven J. Holmes , Cuc K. Huynh , Robert K. Leidy , Paul W. Pastel
发明人： Jeffrey S. Brown , James S. Dunn , Steven J. Holmes , Cuc K. Huynh , Robert K. Leidy , Paul W. Pastel
IPC分类号： H01L29/78 , G03F7/095 , G03F7/38 , H01L21/027 , H01L21/265 , H01L21/311 , H01L21/336 , H01L21/76 , G03C5/00
CPC分类号： H01L29/66492 , G03F7/38 , H01L21/0274 , H01L21/31116 , H01L21/31144 , H01L29/6659 , G03F7/095 , H01L21/26586
摘要： The preferred embodiment of the present invention overcomes the disadvantages of the prior art by using hybrid resist to define a sidewall spacer region and form a new type of sidewall spacer. The preferred method allows for more controlled doping at the gate-source and gate-drain junctions by defining sidewall spacer troughs using hybrid resist. Implants can then be made through the troughs to precisely control the doping at the gate junctions. Additionally, sidewall spacers can then be formed in the sidewall spacer troughs. The dimensions of the sidewall spacers is determined by the hybrid resist and can thus be made smaller than traditional resist processes. Additionally, forming the sidewall spacers using hybrid resist allows for their width to be determined independent of the depth of the gate material.
摘要翻译：本发明的优选实施例通过使用混合抗蚀剂来限定侧壁间隔区并形成新型的侧壁间隔物来克服现有技术的缺点。优选的方法允许通过使用混合抗蚀剂限定侧壁间隔槽来在栅极源极和栅极 - 漏极结处施加更多的受控掺杂。然后可以通过槽制造植入物以精确地控制在浇口结处的掺杂。此外，然后可以在侧壁间隔槽中形成侧壁间隔物。侧壁间隔物的尺寸由混合抗蚀剂确定，因此可以制成比传统的抗蚀剂工艺更小。另外，使用混合抗蚀剂形成侧壁间隔物可以独立于栅极材料的深度确定其宽度。

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