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1. 发明授权

US06230179B1 Finite field multiplier with intrinsic modular reduction 失效
标题翻译：具有内在模块化减少的有限域倍增器
公开(公告)号：US06230179B1
公开(公告)日：2001-05-08
申请号：US08997960
申请日：1997-12-24
申请人： James Douglas Dworkin , Michael John Torla , P. Michael Glaser , Ashok Vadekar , Robert John Lambert , Scott Alexander Vanstone
发明人： James Douglas Dworkin , Michael John Torla , P. Michael Glaser , Ashok Vadekar , Robert John Lambert , Scott Alexander Vanstone
IPC分类号： G06F700
CPC分类号： G06F9/30014 , G06F7/72 , G06F7/722 , G06F7/724 , G06F7/725 , G06F9/30036 , G06F2207/382
摘要： A finite field multiplier with intrinsic modular reduction includes an interface unit (1208) that translates an n bit wide data path to a m bit wide data path where n is less than m. Also included is a finite field data unit (1204) with m bit wide registers that is coupled to a finte field control unit (1202). The finite field control unit (1202) includes a microsequencer (1402) and a finite state machine multiplier (1404). The microsequencer (1402) controls the finite state machine multiplier (1404) which performs a finite field multiply operation with intrinsic modular reduction and presents a finite field multiplication product to the finite field data unit (1204).
摘要翻译：具有本征模块化减少的有限域乘法器包括将n位宽数据路径转换为n小于m的m位宽数据路径的接口单元（1208）。还包括具有m位宽寄存器的有限域数据单元（1204），其耦合到finte域控制单元（1202）。有限场控制单元（1202）包括微定序器（1402）和有限状态机乘法器（1404）。微定序器（1402）控制有限状态机乘法器（1404），其执行具有本征模块化减少的有限域乘法运算，并向有限场数据单元（1204）呈现有限域乘法乘积。

2. 发明授权

US06199086B1 Circuit and method for decompressing compressed elliptic curve points 失效
标题翻译：用于解压缩压缩椭圆曲线点的电路和方法
公开(公告)号：US06199086B1
公开(公告)日：2001-03-06
申请号：US08997959
申请日：1997-12-24
申请人： James Douglas Dworkin , Michael John Torla , P. Michael Glaser , Ashok Vadekar , Robert John Lambert , Scott Alexander Vanstone
发明人： James Douglas Dworkin , Michael John Torla , P. Michael Glaser , Ashok Vadekar , Robert John Lambert , Scott Alexander Vanstone
IPC分类号： G06F772
CPC分类号： G06F7/725
摘要： An elliptic curve (EC) processor circuit (120) comprising a finite field arithmetic logic unit (122), operation registers (124) an EC control unit (123) and a register file (127). A storage element (250) is coupled to the finite field arithmetic logic unit (122). The EC control unit (123) controls the various components of the EC processor circuit (120) to decompress a compressed one-bit representation of a Y coordinate of an elliptic curve point (X, Y). The EC control unit (123) controls the use of the operation register (124), the storage element (250) and the finite field arithmetic logic unit (122) to recursively compute the decompressed version of the compressed Y coordinate based upon the X coordinate and the compressed one-bit representation of the Y coordinate. The circuit and method employ minimal additional hardware and processing in an EC processor circuit (120).
摘要翻译：椭圆曲线（EC）处理器电路（120）包括有限域算术逻辑单元（122），操作寄存器（124），EC控制单元（123）和寄存器文件（127）。存储元件（250）耦合到有限域算术逻辑单元（122）。 EC控制单元（123）控制EC处理器电路（120）的各个组件来解压缩椭圆曲线点（X，Y）的Y坐标的压缩的一位表示。 EC控制单元（123）控制操作寄存器（124），存储元件（250）和有限域算术逻辑单元（122）的使用，以基于X坐标递归地计算压缩的Y坐标的解压缩版本和Y坐标的压缩一位表示。电路和方法在EC处理器电路（120）中采用最小的附加硬件和处理。

3. 发明授权

US5852730A Hybrid instruction set for versatile digital signal processing system 失效
标题翻译：用于通用数字信号处理系统的混合指令集
公开(公告)号：US5852730A
公开(公告)日：1998-12-22
申请号：US764429
申请日：1996-12-12
申请人： John Michael Buss , James Douglas Dworkin , Stephen Lee Smith
发明人： John Michael Buss , James Douglas Dworkin , Stephen Lee Smith
IPC分类号： H03H17/04 , H03H17/06 , H04B1/707 , H04B1/7103 , H04B1/7115 , G06F9/40
CPC分类号： H04B1/707 , H04B1/7103 , H04B1/7115 , H04B2201/7071
摘要： A programmable versatile digital signal processing system architecture (FIG. 5) allows the implementation of functions for transmitting and receiving a variety of narrow and wide-band communication signaling schemes. The flexibility of the architecture (FIG. 5) makes it possible to receive and transmit many different spectral communication signals in real time by implementing signal processing functions such as filtering, spreading, de-spreading, rake filtering, and equalization under the direction of program instructions (1300, 1400, 1500, 1600).
摘要翻译：可编程通用数字信号处理系统架构（图5）允许实现用于发送和接收各种窄带和宽带通信信令方案的功能。架构的灵活性（图5）使得可以通过在程序的方向上实现诸如滤波，扩展，解扩，耙滤波和均衡之类的信号处理功能来实时地接收和发送许多不同的频谱通信信号说明书（1300,1400,1500,1600）。

4. 发明授权

US5640336A Computational array and method for calculating multiple terms of a polynomial in a single computing element 失效
标题翻译：用于计算单个计算元素中多项式的多项的计算阵列和方法
公开(公告)号：US5640336A
公开(公告)日：1997-06-17
申请号：US581800
申请日：1996-01-02
申请人： James Douglas Dworkin , John Michael Buss
发明人： James Douglas Dworkin , John Michael Buss
IPC分类号： G06F7/552 , G06F7/38 , G06F7/52
CPC分类号： G06F7/552 , G06F2207/5523
摘要： A computational array (120) includes at least one computing element (130) that calculates multiple terms in a polynomial. The computing element (130) obtains an input value of each variable in each of the multiple terms and a subscript uniquely identifying the variable, The computing element (130) reads a term identifier and an exponent corresponding to the variable at a memory location based on the subscript, The computing element (130) multiplies the input value by a selected weight value and multiplies the input value by itself a number of times based on the exponent and stores the result at a memory location corresponding to the term identifier. The computing element (130) calculates multiple terms by distinguishing each of the terms with the term identifier.
摘要翻译：计算阵列（120）包括计算多项式中的多个项的至少一个计算元件（130）。计算元件（130）获得多个项中的每一个中的每个变量的输入值，以及唯一地标识变量的下标。计算元件（130）基于以下内容读取与存储器位置处的变量相对应的项目标识符和指数下标，计算元件（130）将输入值乘以所选择的权重值，并且基于指数将输入值本身乘以多次，并将结果存储在与术语标识符相对应的存储器位置处。计算元件（130）通过将每个术语与术语标识符区分开来计算多个术语。

5. 发明授权

US06356636B1 Circuit and method for fast modular multiplication 失效
标题翻译：快速模数乘法的电路和方法
公开(公告)号：US06356636B1
公开(公告)日：2002-03-12
申请号：US09120580
申请日：1998-07-22
申请人： Robert I. Foster , John Michael Buss , Rodney C. Tesch , James Douglas Dworkin , Michael J. Torla
发明人： Robert I. Foster , John Michael Buss , Rodney C. Tesch , James Douglas Dworkin , Michael J. Torla
IPC分类号： H04L930
CPC分类号： G06F7/728
摘要： A co-processor (44) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier (56) receives sixteen bit data values stored in an A/B RAM (72) and generates a partial product. The generated partial product is summed in an adder (58) with a previous partial product stored in a product RAM (64). A modulo reducer (60) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM (70) stores the data value N that is added in a modulo reducer (60) to the summed value. The co-processor (44) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of &mgr; as is required in the Montgomery Reduction Algorithm.
摘要翻译：协处理器（44）执行计算用于加密或解密数据的模幂等式的数学算法。流水线乘法器（56）接收存储在A / B RAM（72）中的16位数据值，并产生部分乘积。所产生的部分乘积在加法器（58）中与先前的部分乘积存储在乘积RAM（64）中相加。当求和值的特定数据位位置具有逻辑1值时，模减法器（60）使二进制数据值N对齐并相加到求和值。 N RAM（70）将在模减法器（60）中添加的数据值N存储到求和值。协处理器（44）计算福斯特蒙哥马利削减算法，并且减少（A * B mod N）的值，而不必首先按照Montgomery Reduction算法的要求计算mu的值。

6. 发明授权

US06266717B1 System for controlling data exchange between a host device and a processor 失效
标题翻译：用于控制主机设备和处理器之间的数据交换的系统
公开(公告)号：US06266717B1
公开(公告)日：2001-07-24
申请号：US08997964
申请日：1997-12-24
申请人： James Douglas Dworkin , Michael John Torla , Ashok Vadekar
发明人： James Douglas Dworkin , Michael John Torla , Ashok Vadekar
IPC分类号： G06F1314
CPC分类号： G06F9/30014 , G06F7/72 , G06F7/722 , G06F7/724 , G06F7/725 , G06F9/30036 , G06F2207/382
摘要： A system for efficiently controlling the exchange of data between a host bus (190) and an input/output (I/O) register (125) of an elliptic curve (EC) processor (120) having a much wider datapath than that of the host device (100) . A spreading/despreading pattern is determined which spans multiple bit positions of the input/output register (125). In one embodiment, a full combinational circuit (300) is provided to connect a bit position of the host bus (190) to a bit position of the input/output register (125). In another embodiment, a combinational circuit (300) and an intermediate register (410) are provided. In still another embodiment, a spreading-by shifting system (500) is provided which comprises a plurality of subfield modules (520) into which data from the host bus (190) is shifted. The spreading/despreading pattern is achieved through multiplexers (540) connected between the subfield modules (520). In yet another embodiment, a cross bar switch (600) is provided to connect any bit position of the host bus (190) to any bit position of the I/O register 125. In each embodiment, an EC control unit (123) is provided which stores information for the spreading/despreading pattern.
摘要翻译：一种用于有效控制主机总线（190）与椭圆曲线（EC）处理器（120）的输入/输出（I / O）寄存器（125）之间的数据交换的系统，其具有比主机设备（100）。确定跨越输入/输出寄存器（125）的多个位位置的扩展/解扩展模式。在一个实施例中，提供全组合电路（300）以将主机总线（190）的位位置连接到输入/输出寄存器（125）的位位置。在另一个实施例中，提供组合电路（300）和中间寄存器（410）。在另一个实施例中，提供了扩展移位系统（500），其包括多个子场模块（520），来自主机总线（190）的数据被移动到该子场模块中。扩展/解扩模式通过连接在子场模块（520）之间的多路复用器（540）来实现。在另一个实施例中，提供了一种横杆开关（600），用于将主机总线（190）的任何位位置连接到I / O寄存器125的任何位位置。在每个实施例中，EC控制单元（123）提供哪个存储用于扩展/解扩图案的信息。

7. 发明授权

US06259720B1 Versatile digital signal processing system 失效
标题翻译：多功能数字信号处理系统
公开(公告)号：US06259720B1
公开(公告)日：2001-07-10
申请号：US08764344
申请日：1996-12-12
申请人： John Michael Buss , James Douglas Dworkin , Stephen Lee Smith
发明人： John Michael Buss , James Douglas Dworkin , Stephen Lee Smith
IPC分类号： H04B169
CPC分类号： H04B1/707 , H04B1/7103 , H04B1/7115 , H04B2201/7071
摘要： A programmable versatile digital signal processing system architecture (FIG. 5) allows the implementation of functions for transmitting and receiving a variety of narrow and wide-band communication signaling schemes. The flexibility of the architecture (FIG. 5) makes it possible to receive and transmit many different spectral communication signals in real time by implementing signal processing functions such as filtering, spreading, de-spreading, rake filtering, and equalization under the direction of program instructions (FIGS. 13, 14, 15, and 16).
摘要翻译：可编程通用数字信号处理系统架构（图5）允许实现用于发送和接收各种窄带和宽带通信信令方案的功能。架构的灵活性（图5）使得可以通过在程序的方向上实现诸如滤波，扩展，解扩，耙滤波和均衡之类的信号处理功能来实时地接收和发送许多不同的频谱通信信号指令（图13，图14，图15和图16）。

8. 发明授权

US06182104B2 Circuit and method of modulo multiplication 失效
标题翻译：电路和模乘法的方法
公开(公告)号：US06182104B2
公开(公告)日：2001-01-30
申请号：US09120835
申请日：1998-07-22
申请人： Robert I. Foster , John Michael Buss , Rodney C. Tesch , James Douglas Dworkin , Michael J. Torla
发明人： Robert I. Foster , John Michael Buss , Rodney C. Tesch , James Douglas Dworkin , Michael J. Torla
IPC分类号： G06F738
CPC分类号： G06F7/728
摘要： A co-processor (44) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier (56) receives sixteen bit data values stored in an A/B RAM (72) and generates a partial product. The generated partial product is summed in a summer (58) with a previous partial product stored in a product RAM (64). A modulo reducer (60) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM (70) stores the data value N that is added in a modulo reducer (60) to the summed value. The co-processor (44) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of &mgr; as is required in the Montgomery Reduction Algorithm.
摘要翻译：协处理器（44）执行计算用于加密或解密数据的模幂等式的数学算法。流水线乘法器（56）接收存储在A / B RAM（72）中的16位数据值，并产生部分乘积。生成的部分乘积在夏季（58）中与先前的部分积存在产品RAM（64）中相加。当求和值的特定数据位位置具有逻辑1值时，模减法器（60）使二进制数据值N对齐并相加到求和值。 N RAM（70）将在模减法器（60）中添加的数据值N存储到求和值。协处理器（44）计算福斯特蒙哥马利削减算法，并且减少（A * B mod N）的值，而不必首先按照Montgomery Reduction算法的要求计算mu的值。

9. 发明授权

US6009450A Finite field inverse circuit 失效
标题翻译：有限域反向电路
公开(公告)号：US6009450A
公开(公告)日：1999-12-28
申请号：US997943
申请日：1997-12-24
申请人： James Douglas Dworkin , P. Michael Glaser , Michael John Torla , Ashok Vadekar , Robert John Lambert , Scott Alexander Vanstone
发明人： James Douglas Dworkin , P. Michael Glaser , Michael John Torla , Ashok Vadekar , Robert John Lambert , Scott Alexander Vanstone
IPC分类号： G06F7/72 , G06F7/00
CPC分类号： G06F7/726
摘要： A finite field inverse circuit has a finite field data unit (1112) and an inverse control unit (1110). The inverse control unit includes (1110) a k.sub.l and k.sub.u decrementer pair (1108, 1122), a k.sub.l -k.sub.u difference unit (1106), an inverse control finite state machine (1102), and a one-bit memory (1104) coupled to the inverse control finite state machine (1102). The finite field data unit (1112) includes four m bit wide registers that are shift registers designated as B (1120), A (1118), M (1114), and C (1116), where B- is a first register, A- is a second register, M- is a irreducible polynomial register, and C- is a field element register. An the irreducible polynomial is loaded left justified in the M-register, a field element to be inverted is loaded left justified in the C-register, and a single "1" is loaded in an LSB bit of the B-register. The field element is then inverted in 2n+2 system clock cycles where n is a field size associated with the field element.
摘要翻译：有限域逆电路具有有限场数据单元（1112）和逆控制单元（1110）。逆控制单元包括（1110）kl和ku减量器对（1108,1122），kl-ku差分单元（1106），逆控制有限状态机（1102）和耦合到一个比特存储器（1104）的一位存储器到反向有限状态机（1102）。有限域数据单元（1112）包括四个m位宽的寄存器，它们是指定为B（1120），A（1118），M（1114）和C（1116）的移位寄存器，其中B-是第一寄存器，A - 是第二寄存器，M-是不可约多项式寄存器，C是场元素寄存器。在M寄存器中左对齐加载不可约多项式，在C寄存器中左对齐加载要反相的场元素，并在B寄存器的LSB位中加载单个“1”。然后，在2n + 2个系统时钟周期中，场元素被反转，其中n是与场元素相关联的场大小。

10. 发明授权

US6003057A Galois field arithmetic logic unit circuit 失效
标题翻译：伽罗瓦域算术逻辑单元电路
公开(公告)号：US6003057A
公开(公告)日：1999-12-14
申请号：US998376
申请日：1997-12-24
申请人： James Douglas Dworkin , Michael John Torla , Rodney Clair Tesch , Scott Vanstone
发明人： James Douglas Dworkin , Michael John Torla , Rodney Clair Tesch , Scott Vanstone
IPC分类号： G06F7/72 , G06F7/00
CPC分类号： G06F7/724
摘要： A Galois Field arithmetic logic unit (GF ALU) circuit (200) that generates a GF product of size M includes a first and a second input field element register (205, 210), a result field element register (215), a plurality, I, of subfield sets of logic gates (255, 260, 265), a plurality, S, of extension sets of logic gates (270, 275), and 3M switches (135). M is equal to S multiplied by I. A Galois Field of size M, S, and I each has an optimal normal basis. The first and second input field element registers (205, 210) are alternately coupled to the result field element register (215) by the I subfield sets of logic gates (255, 260, 265) in a first configuration and by the S extension sets of logic gates (270, 275) in a second configuration. The 3M switches (135) alternate the first and second configurations.
摘要翻译：产生尺寸M的GF乘积的伽罗瓦域算术逻辑单元（GF ALU）电路（200）包括第一和第二输入场单元寄存器（205,210），结果场单元寄存器（215），多个， I，逻辑门（255,260,265）的子场集合，多个逻辑门（270,275）的扩展组S和3M开关（135）。 M等于S乘以I.尺寸M，S和I的伽罗瓦域各具有最佳的正常基础。第一和第二输入场元件寄存器（205,210）通过第一配置的逻辑门（255,260,265）的I子场集合和S扩展集合交替地耦合到结果场元素寄存器（215）的第二配置中的逻辑门（270,275）。 3M开关（135）交替第一和第二配置。

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