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1. 发明授权

US06779011B2 System for performing multiplication and division in GF(22M) 失效
标题翻译：在GF（22M）中执行乘法和除法的系统
公开(公告)号：US06779011B2
公开(公告)日：2004-08-17
申请号：US09796051
申请日：2001-02-28
申请人： Lih-Jyh Weng , Dana Hall , Christine Imrich
发明人： Lih-Jyh Weng , Dana Hall , Christine Imrich
IPC分类号： G06F772
CPC分类号： G06F7/726
摘要： A system determines the multiplicative inverse of A∈GF(22M) by representing A using a selected basis in which basis elements are squares of one another, and performing various operations that involve raising A to powers of 2 as cyclic rotations of A. The system also performs multiplication operations over GF(22M) or subfields thereof by calculating the coefficients of the product of two elements A and B that are represented using the selected basis as combinations of the coefficients of cyclically rotated versions of A and B. The system further utilizes a relatively small look-up table that contains the multiplicative inverses of selected elements of a subfield of GF(22M). The system may then cyclically rotate the multiplicative inverse values read from the table to produce the multiplicative inverses of the remaining elements of the subfield. Thereafter, as applicable, the system further manipulates the multiplicative inverse of the subfield element, to produce the multiplicative inverse of the desired element of GF(22M). Using the selected basis, elements of GF(22M) that are elements of the subfields have m lowest-order coefficients that are duplicates of the m highest order coefficients. Each element in the look-up table can thus be represented using only m bits, and the table can be entered with m bits.
摘要翻译：系统通过使用选择的基础来确定A∈GF（2 <2M>）的乘法逆，其中基元是彼此的平方，并且执行涉及将A提高到2的幂的各种操作作为A的循环旋转该系统还通过计算使用所选择的基础表示的两个元素A和B的乘积的系数作为A的循环旋转版本的系数的组合来执行GF（2 <2M>）或其子场的乘法运算，以及该系统进一步利用一个相对较小的查找表，其中包含GF（2 <2M>）的子域的选定元素的乘法反转。然后，系统可以循环地旋转从表读取的乘法反向值，以产生子场的剩余元素的乘法反转。此后，在适用的情况下，系统进一步操纵子场元素的乘法逆，以产生GF（2 <2M>）的期望元素的乘法逆。使用所选择的基础，作为子场的元素的GF（2 <2M>）的元素具有m个最高阶系数的m个最低阶系数。因此，可以仅使用m位来表示查找表中的每个元素，并且可以以m位输入表。

2. 发明授权

US06662201B1 Modular arithmetic apparatus and method having high-speed base conversion function 有权
标题翻译：具有高速基本转换功能的模块化运算装置和方法
公开(公告)号：US06662201B1
公开(公告)日：2003-12-09
申请号：US09699481
申请日：2000-10-31
申请人： Shinichi Kawamura
发明人： Shinichi Kawamura
IPC分类号： G06F772
CPC分类号： G06F7/729 , G06F7/723
摘要： In a modular arithmetic apparatus including a plurality of product-sum circuits having a modular arithmetic function and parallelly arranged, and a correction term calculation unit for calculating a correction term to be used for modular arithmetic operation in the product-sum circuits, the correction term calculation unit sequentially calculates the correction term in units of bits, and each of the product-sum circuits sequentially reflects the correction term calculated by the correction term calculation unit and performs base conversion or base extension.
摘要翻译：在包括具有模数运算功能并并列布置的多个积和电路的模运算装置中，以及校正项计算单元，用于计算乘积和电路中用于模运算的校正项，校正项计算单元以位为单位顺序地计算校正项，并且乘积和电路中的每一个顺序地反映由校正项计算单元计算的校正项，并执行基本转换或基本扩展。

3. 发明授权

US06826586B2 Method for efficient computation of point doubling operation of elliptic curve point scalar multiplication over finite fields F(2m) 有权
标题翻译：椭圆曲线点标量乘积有限计算方法有限域F（2m）
公开(公告)号：US06826586B2
公开(公告)日：2004-11-30
申请号：US09738571
申请日：2000-12-15
申请人： Sheueling Chang
发明人： Sheueling Chang
IPC分类号： G06F772
CPC分类号： G06F7/725
摘要： The present invention provides a method for performing a point doubling operation with only one modular division and no multiply per operation. As a result, the invention reduces the number of mathematical operations needed to perform point doubling operations in elliptic curve computation. An elliptic curve cryptosystem using the present invention can be made to operate more efficiently using the present invention. An elliptic curve crypto-accelerator can be implemented using the present invention to dramatically enhance the performance of the elliptic curve cryptosystem. The invention derives the slope of a curve independently of the y-coordinate. By avoiding the calculation of the y term, one additional multiply is eliminated from each point-doubling operation. Using the invention, n consecutive point doublings can be reduced to n modular divisions and 1 multiply. This avoids the 2n multiplies of prior art approaches.
摘要翻译：本发明提供了一种仅用一个模块划分进行点加倍运算的方法，并且每个运算不进行乘法运算。结果，本发明减少了在椭圆曲线计算中执行点加倍运算所需的数学运算的数量。使用本发明的椭圆曲线密码系统可以使用本发明更有效地进行操作。可以使用本发明来实现椭圆曲线加密器，以显着增强椭圆曲线密码系统的性能。本发明独立于y坐标得出曲线的斜率。通过避免y项的计算，从每个加倍运算中消除一个附加乘法。使用本发明，可以将n个连续点叠加减少到n个模块化分区，并将1乘法运算。这避免了现有技术方法的2n倍。

4. 发明授权

US06636882B1 Means and method for performing multiplication 有权
标题翻译：用于执行乘法的方法和方法
公开(公告)号：US06636882B1
公开(公告)日：2003-10-21
申请号：US09482623
申请日：2000-01-14
申请人： Wei-Ming Su , Shin Yung Chen Banyan , Yi-Lin Lai
发明人： Wei-Ming Su , Shin Yung Chen Banyan , Yi-Lin Lai
IPC分类号： G06F772
CPC分类号： G06F7/724
摘要： A multiplier for obtaining the product of elements in a Galois Field. The multiplier performs the multiplication of two n-bit elements, A(an-1, an-2, . . . , a3, a2, a1, a0) and B(bn-1, bn-2, . . . , b3, b2, b1, b0) in the Galois Field to yield the product C(cn-1, cn-2, . . . , c3, c2, c1, c0), wherein n≧1 ai(i=0˜n-1), bj(j=0˜n-1), and ck(k=O˜n-1) are all binary bits. The multiplier includes: an AND planer, for performing an AND logic operation of every bit ai in A(an-1, an-2, . . . , a3, a2, a1, a0) and every bit bj in B(bn-1, bn-2, . . . , b3, b2, b1, b0) to obtain (an-1bn-1, an-1bn-2, . . . , an-1b0, an-2bn-1, an-2bn-2, . . . , an-2b0, a0bn-1, a0bn-2, . . . , a0b0); and an XOR planer, for performing an XOR logic operation of the output from the AND planer to obtain C(cn-1, cn-2, . . . , c3, c2, c1, c0).
摘要翻译：用于获得伽罗瓦域中元素乘积的乘数。乘法器执行两个n位元素A（an-1，an-2，...，a3，a2，a1，a0）和B（bn-1，bn-2，...，b3 ，b2，b1，b0），以产生乘积C（cn-1，cn-2，...，c3，c2，c1，c0），其中n> = 1 ai（i = 0〜n -1），bj（j = 0〜n-1）和ck（k = 0〜n-1）都是二进制位。乘法器包括：AND平面，用于执行A（an-1，an-2，...，a3，a2，a1，a0）中的每个位ai的AND逻辑运算以及B（bn- 1，bn-2，...，b3，b2，b1，b0），得到（an-1bn-1，a-1bn-2，...，a-1b0，an-20bn-1， -2，...，a-2b0，a0bn-1，a0bn-2，...，a0b0）; 和XOR刨床，用于对AND刨床的输出执行XOR逻辑运算，以获得C（cn-1，cn-2，...，c3，c2，c1，c0）。

5. 发明授权

US06523054B1 Galois field arithmetic processor 失效
标题翻译：伽罗瓦域算术处理器
公开(公告)号：US06523054B1
公开(公告)日：2003-02-18
申请号：US09437473
申请日：1999-11-10
申请人： Shunsuke Kamijo
发明人： Shunsuke Kamijo
IPC分类号： G06F772
CPC分类号： G06F7/724
摘要： A practical Galois field arithmetic processor capable of high-speed operation with a simple configuration is disclosed. The processor comprises an instruction decoder, an arithmetic unit including a Galois field vector adder, a Galois field vector multiplier and a Galois exponent adder-subtractor for executing the Galois field arithmetic operation on first and second operands. In the case where the arithmetic unit includes at least a Galois field vector adder and a Galois field vector multiplier, an exponent-vector conversion circuit is provided for converting the second operand from an exponential expression into a vectorial expression, and an instruction is provided for performing the Galois field operation on the vectorially expressed first operand and the exponentially expressed second operand. With this configuration, in the case where the vectorially expressed data is input as the first operand and the exponentially expressed data is input as the second operand, the second operand is converted into a vectorial expression by the conversion circuit, after which the arithmetic operation is performed in the Galois field vector adder or the Galois vector multiplier.
摘要翻译：公开了一种能够以简单配置进行高速操作的实用的伽罗瓦域算术处理器。处理器包括指令解码器，包括伽罗瓦域向量加法器，伽罗瓦域向量乘法器和用于在第一和第二操作数上执行伽罗瓦域算术运算的伽罗瓦指数加法器 - 减法器的运算单元。在运算单元至少包括伽罗瓦域向量加法器和伽罗瓦域向量乘法器的情况下，提供指数矢量转换电路，用于将第二操作数从指数表达式转换为矢量表达式，并且提供指令对矢量表达的第一操作数和指数表达的第二操作数执行Galois场操作。利用这种配置，在将第二操作数作为第一操作数输入向量表达数据并且将指数表达数据作为第二操作数输入的情况下，通过转换电路将第二操作数转换为向量表达式，之后算术运算为在伽罗瓦域矢量加法器或Galois矢量乘法器中执行。

6. 发明授权

US06609142B1 Method of performing multiplication with accumulation in a Galois body 有权
标题翻译：在伽罗瓦身体中进行累积的乘法的方法
公开(公告)号：US06609142B1
公开(公告)日：2003-08-19
申请号：US09621891
申请日：2000-07-20
申请人： Pierre-Yvan Liardet
发明人： Pierre-Yvan Liardet
IPC分类号： G06F772
CPC分类号： G06F7/724
摘要： A method is provided for performing multiplication with accumulation in a Galois Field on a first data, a second data, and a third data, with each of the data being coded on 2 n bits. A first multiplication, in the sense of the arithmetic of a Galois Field, is performed on the first data and the n lowest weight bits of the second data to produce a first intermediate result coded on 3 n bits, and a first addition, in the sense of the arithmetic of a Galois Field, is performed on the third data and the first intermediate result to produce a second intermediate result on 3 n bits. A second multiplication, in the sense of the arithmetic of a Galois Field, is performed on the first data and the n highest weight bits of the second data to produce a third intermediate result on 3 n bits, and a second addition, in the sense of the arithmetic of a Galois Field, is performed on the 2 n highest weight bits of the second intermediate result and the third intermediate result to produce a fourth intermediate result coded on 3 n bits. In a preferred embodiment, the 2 n highest weight bits of the second intermediate result are stored in an intermediate register and the n lowest weight bits of the second intermediate result in an output register.
摘要翻译：提供了一种用于在第一数据，第二数据和第三数据上执行与伽罗瓦域中的累加相乘的方法，其中每个数据被编码为2 n位。在Galois域的算术意义上的第一乘法对第一数据和第二数据的n个最低加权比特执行，以产生以3 n比特编码的第一中间结果，并且在第对第三数据和第一中间结果执行Galois域的算术感，以产生3 n比特的第二中间结果。在Galois域的算术意义上的第二乘法对第二数据的第一数据和n个最高加权比特执行，以在3n比特上产生第三中间结果，并且在该意义上产生第二加法在第二中间结果和第三中间结果的2 n个最高权重位上执行Galois域的算术，以产生以3 n比特编码的第四中间结果。在优选实施例中，第二中间结果的2 n个最高权重位被存储在中间寄存器中，并且第二中间值的n个最低权重位产生输出寄存器。

7. 发明授权

US06470369B1 Euclid mutual division arithmetic circuit and processing circuit 失效
标题翻译：欧几里得相互运算电路和处理电路
公开(公告)号：US06470369B1
公开(公告)日：2002-10-22
申请号：US09421672
申请日：1999-10-20
申请人： Maki Ikegami
发明人： Maki Ikegami
IPC分类号： G06F772
CPC分类号： G06F7/726
摘要： The Euclid mutual division arithmetic circuit relating to the present invention comprises first, second, and third register portions and control portion. Each register portion is constituted so as to be able to selectively perform a Euclid mutual division, perform Euclid mutual division using a divisor and dividend, supply the divisor used in the Euclid mutual division operation, and supply the dividend used in the Euclid mutual division operation. The control portion operates so that, in a kth operation, the first register portion supplies the dividend, the second register portion performs the division operation, and the third register portion supplies the divisor supplying function; in a (k+1)th operation, the first register performs the division operation, the second register portion supplies the divisor, and the third register portion performs the dividend. In a (k+2)th operation, the first register portion supplies the divisor, the second register supplies the dividend, and the third register portion performs the division operation. This Euclid mutual division arithmetic circuit can operate at high speeds because a subsequent operation is performed without data transfer, once a first operation is complete.
摘要翻译：涉及本发明的欧几里德相互分割运算电路包括第一，第二和第三寄存器部分和控制部分。每个寄存器部分被构造成能够选择性地执行欧几里德相互划分，使用除数和除数执行欧几里德相互划分，提供在欧几里德相互分割操作中使用的除数，并且提供在欧几里德相互分割操作中使用的被除数。控制部分操作，使得在第k个操作中，第一寄存器部分提供除数，第二寄存器部分执行除法运算，第三寄存器部分提供除数提供功能; 在第（k + 1）操作中，第一寄存器执行除法运算，第二寄存器部分提供除数，并且第三寄存器部分执行除数。在第（k + 2）操作中，第一寄存器部分提供除数，第二寄存器提供除数，第三寄存器部分进行除法运算。一旦第一次操作完成，该欧几里德相互分割算术电路可以高速运行，因为在不进行数据传送的情况下执行后续操作。

8. 发明授权

US06415310B1 Remainder calculating method, modular-multiplication method, remainder calculating apparatus, modular-multiplication apparatus and recording medium 失效
标题翻译：剩余计算方法，乘法法，余数计算装置，模数乘法装置和记录介质
公开(公告)号：US06415310B1
公开(公告)日：2002-07-02
申请号：US09412502
申请日：1999-10-05
申请人： Masahiko Takenaka , Naoya Torii
发明人： Masahiko Takenaka , Naoya Torii
IPC分类号： G06F772
CPC分类号： G06F7/728
摘要： In a remainder calculating method and a modular-multiplication method on the basis of a Montgomery method, a number expressed by N (N=c2d±1) is used as a divisor N. In order to calculate a remainder in the case of dividing a dividend Y by a divisor N on the basis of a Montgomery method, a number expressed by a condition of N=c2d−1 is used as the divisor N, and the following steps are repeatedly carried out; the steps includes: a step of adding a product of a least digit value yo of the dividend Y and c to a lower d-bit position of the dividend Y; and a step of setting a portion excluding the least digit of the additive result as a next dividend.
摘要翻译：在基于蒙哥马利方法的余数计算方法和模乘法中，使用N（N = c2d±1）表示的数作为除数N.为了计算在除数除数N由蒙哥马利方法计算，由N = c2d-1的条件表示的数字用作除数N，并重复执行以下步骤：所述步骤包括：将除数Y和c的最小数字值yo的乘积加到所述除数Y的较低d位位置的步骤; 以及将除了加法结果的最小数字之外的部分设置为下一个分红的步骤。

9. 发明授权

US06317769B1 Apparatus for calculating of Bc (mod n) with repeatedly shifting a holding value 失效
标题翻译：用于计算重复移动保持值的Bc（mod n）的装置
公开(公告)号：US06317769B1
公开(公告)日：2001-11-13
申请号：US09219942
申请日：1998-12-23
申请人： Yoshinao Kobayashi , Akashi Satoh , Hideto Nijima
发明人： Yoshinao Kobayashi , Akashi Satoh , Hideto Nijima
IPC分类号： G06F772
CPC分类号： G06F7/723
摘要： An apparatus to calculate a remainder of Bc modulo n at high speed with minimum hardware resources, while securing safety of a key comprises: a first circuit to execute a process of calculating B (mod n) and holding the calculation result B1 and to repeat a process of shifting a holding value and calculating a value congruent to the shifted holding value modulo n and holding the calculation result; a first register for storing the B1 as an initial value; a second circuit to cumulate the calculation result of the first circuit when a value of a bit at a predetermined position of the first register is equal to 1; a second register to store 1 as an initial value; a C output circuit to output C; a third circuit to cumulate the calculation result of the first circuit when an output value from said C output circuit is equal to 1 and a value of a bit at a predetermined position of the second register is equal to 1. The bit at the predetermined position of the first register and the second register shifts from LSB to MSB of their stored values. When a process for MSB of a value stored by the first register ends, a value congruent to the cumulated result in the second circuit modulo n is set as the holding value and stored into the first register, the output of the C output circuit changes to a value shifted from LSB to MSB of the C, and when the output of the C output circuit is 1, a value congruent to the cumulated result in the third circuit modulo n is stored in the second register.
摘要翻译：一种用于以最小的硬件资源以高速计算Bc模n的余数的装置，同时确保密钥的安全性包括：执行计算B（mod n）并保持计算结果B1的过程的第一电路，并重复移动保持值并计算与移位的保持值模n相等的值并保持计算结果的处理; 用于存储B1作为初始值的第一寄存器; 当第一寄存器的预定位置处的位的值等于1时，累加第一电路的计算结果的第二电路; 第二个寄存器，用于存储1作为初始值; C输出电路输出C; 当来自所述C输出电路的输出值等于1并且所述第二寄存器的预定位置处的位的值等于1时，累加所述第一电路的计算结果的第三电路。所述预定位置处的所述位的第一个寄存器和第二个寄存器从LSB到MSB的存储值。当由第一寄存器存储的值的MSB的处理结束时，将第二电路模n的累积结果的值设置为保持值并存储到第一寄存器中，C输出电路的输出变为 C的值从LSB移动到MSB，当C输出电路的输出为1时，与第n个电路模n的累积结果一致的值存储在第2寄存器中。

10. 发明授权

US06820105B2 Accelerated montgomery exponentiation using plural multipliers 失效
标题翻译：使用多个乘数加速蒙哥马利乘数
公开(公告)号：US06820105B2
公开(公告)日：2004-11-16
申请号：US09849853
申请日：2001-05-04
申请人： David M. Blaker
发明人： David M. Blaker
IPC分类号： G06F772
CPC分类号： G06F9/3879 , G06F7/728 , G06F21/123 , G06F21/72 , H04L9/0877 , H04L2209/125
摘要： Montgomery exponentiators and methods modulo exponentiate a generator (g) to a power of an exponent (e). The Montgomery exponentiators and methods include a first multiplier that is configured to repeatedly square a residue of the generator, to produce a series of first multiplier output values at a first multiplier output. A second multiplier is configured to multiply selected ones of the series of first multiplier output values that correspond to a bit of the exponent that is binary one, by a partial result, to produce a series of second multiplier output values at a second multiplier output. By providing two multipliers that are serially coupled as described above, Montgomery exponentiation can be accelerated.
摘要翻译：蒙哥马利指数和方法将发电机（g）取幂为指数（e）的幂。蒙哥马利指数和方法包括第一乘法器，其被配置为重复地平方发生器的残差，以在第一乘法器输出处产生一系列第一乘法器输出值。第二乘法器被配置为通过部分结果将对应于二进制指数的比特的一系列第一乘法器输出值中的选定的乘法器乘以第二乘法器输出的一系列第二乘法器输出值。通过提供如上所述串联耦合的两个乘法器，可以加速蒙哥马利乘数。

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