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1. 发明授权

US08344346B2 Semiconductor device having resistive device 有权
标题翻译：具有电阻器件的半导体器件
公开(公告)号：US08344346B2
公开(公告)日：2013-01-01
申请号：US13073521
申请日：2011-03-28
申请人： Seung Beom Baek , Ja Chun Ku , Young Ho Lee , Jin Hyock Kim
发明人： Seung Beom Baek , Ja Chun Ku , Young Ho Lee , Jin Hyock Kim
IPC分类号： H01L29/02 , H01L29/06 , G11C11/00
CPC分类号： H01L27/249 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146
摘要： A semiconductor memory device includes a plurality of word lines vertically formed on a surface of a semiconductor substrate, where each pair of the plurality of word lines form a set of word lines, a bit line formed parallel to the surface of the semiconductor substrate and disposed in plurality stacked between the word lines of each pair constituting the one set of word lines, and unit memory cells disposed between respective ones of the bit lines and an adjacent one of the pair of word lines of said one of the word line sets.
摘要翻译：半导体存储器件包括垂直形成在半导体衬底的表面上的多个字线，其中每对多条字线形成一组字线，平行于半导体衬底的表面形成的位线，多个堆叠在构成所述一组字线的每一对的字线之间，以及设置在所述一个字线组中的所述位线中的相应位线与所述一对字线中的相邻一个之间的单元存储单元。

2. 发明申请

US20120231635A1 TEMPLATE DERIVATIVE FOR FORMING ULTRA-LOW DIELECTRIC LAYER AND METHOD OF FORMING ULTRA-LOW DIELECTRIC LAYER USING THE SAME 有权
公开(公告)号：US20120231635A1
公开(公告)日：2012-09-13
申请号：US13475237
申请日：2012-05-18
申请人： Sung Kyu MIN , Ja Chun KU , Sang Tae AHN , Chai O CHUNG , Hyeon Ju AN , Hyo Seok LEE , Eun Jeong KIM , Chan Bae KIM
发明人： Sung Kyu MIN , Ja Chun KU , Sang Tae AHN , Chai O CHUNG , Hyeon Ju AN , Hyo Seok LEE , Eun Jeong KIM , Chan Bae KIM
IPC分类号： H01L21/31 , C07H23/00
CPC分类号： H01L21/31695 , C08B37/0012 , C08L83/04 , C09D105/16 , C09D183/02 , H01L21/02126 , H01L21/02203 , H01L21/02208 , H01L21/02282 , H01L21/02337
摘要： A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer.

3. 发明授权

US08202807B2 Template derivative for forming ultra-low dielectric layer and method of forming ultra-low dielectric layer using the same 有权
标题翻译：用于形成超低介电层的模板衍生物和使用其形成超低介电层的方法
公开(公告)号：US08202807B2
公开(公告)日：2012-06-19
申请号：US11964950
申请日：2007-12-27
申请人： Sung Kyu Min , Ja Chun Ku , Chan Bae Kim , Sang Tae Ahn , Chai O Chung , Hyeon Ju An , Hyo Seok Lee , Eun Jeong Kim
发明人： Sung Kyu Min , Ja Chun Ku , Chan Bae Kim , Sang Tae Ahn , Chai O Chung , Hyeon Ju An , Hyo Seok Lee , Eun Jeong Kim
IPC分类号： H01L21/31
CPC分类号： H01L21/31695 , C08B37/0012 , C08L83/04 , C09D105/16 , C09D183/02 , H01L21/02126 , H01L21/02203 , H01L21/02208 , H01L21/02282 , H01L21/02337
摘要： A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer.
摘要翻译：使用反应性环糊精衍生物或反应性葡萄糖衍生物作为形成超低介电层的模板衍生物。由反应性环糊精衍生物或用Si-H封端的反应性葡萄糖衍生物形成层，然后在过氧化氢气氛中固化形成超低介电层。

4. 发明申请

US20090061622A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING LIFTING OF AMORPHOUS CARBON LAYER FOR HARD MASK 审中-公开
标题翻译：制造半导体器件的方法，用于防止非磁性层对硬掩模的提升
公开(公告)号：US20090061622A1
公开(公告)日：2009-03-05
申请号：US12045174
申请日：2008-03-10
申请人： Sang Tae AHN , Ja Chun KU , Eun Jeong KIM
发明人： Sang Tae AHN , Ja Chun KU , Eun Jeong KIM
IPC分类号： H01L21/44
CPC分类号： H01L21/76862 , H01L21/0332 , H01L21/32139 , H01L21/76832
摘要： In a method for manufacturing a semiconductor device, a conductive layer is formed on a semiconductor substrate. A surface of the conductive layer is then treated by plasma. After the conductive layer is treated, an amorphous carbon layer for a hard mask is formed on the surface of the conductive layer that has been treated by the plasma.
摘要翻译：在半导体器件的制造方法中，在半导体衬底上形成导电层。然后通过等离子体处理导电层的表面。在处理导电层之后，在已经通过等离子体处理的导电层的表面上形成用于硬掩模的无定形碳层。

5. 发明授权

US06316349B1 Method for forming contacts of semiconductor devices 失效
标题翻译：形成半导体器件的触点的方法
公开(公告)号：US06316349B1
公开(公告)日：2001-11-13
申请号：US09438048
申请日：1999-11-10
申请人： Jeong Ho Kim , Jae Ok Ryu , Ja Chun Ku , Jin Woong Kim , Si Bum Kim , Su Jin Oh
发明人： Jeong Ho Kim , Jae Ok Ryu , Ja Chun Ku , Jin Woong Kim , Si Bum Kim , Su Jin Oh
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/3144 , H01L21/76801 , H01L21/76834 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for forming contacts of a semiconductor device. In accordance with the invention, an oxidized silicon-rich nitride film is used as an etch barrier film for a self-aligned contact (SAC) process. Accordingly, the oxidized silicon-rich nitride film exhibits less stress, as compared to an LPCVD nitride film, thereby being capable of avoiding a degradation in the characteristics of the devices finally produced or distortion of the wafer used. There is no formation of cracks occurring in the nitride film during a subsequent thermal process. It is also unnecessary to conduct an additional reflection preventing process. Accordingly, the entire process is simplified. It is also possible to improve a decrease in the operating speed of the devices due to a parasitic capacitance existing among conductive lines because the oxidized silicon-rich nitride film has a low dielectric constant, as compared to nitride films. No damage occurs in the oxidized silicon-rich nitride film, so that it is possible to prevent the substrate from being damaged.
摘要翻译：公开了一种形成半导体器件的接触的方法。根据本发明，氧化富硅氮化物膜用作自对准接触（SAC）工艺的蚀刻阻挡膜。因此，与LPCVD氮化物膜相比，氧化富硅氮化物膜的应力显示较小，从而能够避免最终产生的器件的特性劣化或所使用的晶片的变形。在随后的热处理中，在氮化物膜中不会形成裂缝。也不需要进行附加的防反射处理。因此，整个过程被简化。与氮化膜相比，由于氧化富硅的氮化物膜具有低的介电常数，所以可以改善由于导电线中存在的寄生电容而引起的器件的工作速度的降低。在氧化富硅的氮化物膜中不会发生损伤，从而可以防止衬底损坏。

6. 发明授权

US08349636B2 Method of manufacturing a phase change memory device using a cross patterning technique 有权
标题翻译：使用交叉图案化技术制造相变存储器件的方法
公开(公告)号：US08349636B2
公开(公告)日：2013-01-08
申请号：US12834141
申请日：2010-07-12
申请人： Jang Uk Lee , Kang Sik Choi , Hae Chan Park , Jin Hyock Kim , Ja Chun Ku
发明人： Jang Uk Lee , Kang Sik Choi , Hae Chan Park , Jin Hyock Kim , Ja Chun Ku
IPC分类号： H01L21/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683
摘要： A method of manufacturing a phase change memory device is provided. A first insulating layer having a plurality of metal word lines spaced apart at a constant distance is formed on a semiconductor substrate. A plurality of line structures having a barrier metal layer, a polysilicon layer and a hard mask layer are formed to be overlaid on the plurality of metal word lines. A second insulating layer is formed between the line structures. Cross patterns are formed by etching the hard mask layers and the polysilicon layers of the line structures using mask patterns crossed with the metal word lines. A third insulating layer is buried within spaces between the cross patterns. Self-aligned phase change contact holes are formed and at the same time, diode patterns formed of remnant polysilicon layers are formed by selectively removing the hard mask layers constituting the cross patterns.
摘要翻译：提供一种制造相变存储器件的方法。在半导体衬底上形成具有以恒定距离隔开的多个金属字线的第一绝缘层。形成具有阻挡金属层，多晶硅层和硬掩模层的多个线结构以覆盖在多个金属字线上。在线路结构之间形成第二绝缘层。通过使用与金属字线交叉的掩模图案蚀刻线结构的硬掩模层和多晶硅层来形成交叉图案。第三绝缘层埋在交叉图案之间的空间内。形成自对准的相变接触孔，同时，通过选择性地去除构成交叉图案的硬掩模层，形成由剩余多晶硅层形成的二极管图案。

7. 发明申请

US20110143477A1 METHOD OF MANUFACTURING A PHASE CHANGE MEMORY DEVICE USING A CROSS PATTERNING TECHNIQUE 有权
标题翻译：使用交叉图形技术制造相位变化记忆装置的方法
公开(公告)号：US20110143477A1
公开(公告)日：2011-06-16
申请号：US12834141
申请日：2010-07-12
申请人： Jang Uk LEE , Kang Sik CHOI , Hae Chan PARK , Jin Hyock KIM , Ja Chun KU
发明人： Jang Uk LEE , Kang Sik CHOI , Hae Chan PARK , Jin Hyock KIM , Ja Chun KU
IPC分类号： H01L21/28
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683
摘要： A method of manufacturing a phase change memory device is provided. A first insulating layer having a plurality of metal word lines spaced apart at a constant distance is formed on a semiconductor substrate. A plurality of line structures having a barrier metal layer, a polysilicon layer and a hard mask layer are formed to be overlaid on the plurality of metal word lines. A second insulating layer is formed between the line structures. Cross patterns are formed by etching the hard mask layers and the polysilicon layers of the line structures using mask patterns crossed with the metal word lines. A third insulating layer is buried within spaces between the cross patterns. Self-aligned phase change contact holes are formed and at the same time, diode patterns formed of remnant polysilicon layers are formed by selectively removing the hard mask layers constituting the cross patterns.
摘要翻译：提供一种制造相变存储器件的方法。在半导体衬底上形成具有以恒定距离隔开的多个金属字线的第一绝缘层。形成具有阻挡金属层，多晶硅层和硬掩模层的多个线结构以覆盖在多个金属字线上。在线路结构之间形成第二绝缘层。通过使用与金属字线交叉的掩模图案蚀刻线结构的硬掩模层和多晶硅层来形成交叉图案。第三绝缘层埋在交叉图案之间的空间内。形成自对准的相变接触孔，同时，通过选择性地去除构成交叉图案的硬掩模层，形成由剩余多晶硅层形成的二极管图案。

8. 发明申请

US20100261355A1 METHOD FOR FORMING A HIGH QUALITY INSULATION LAYER ON A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：在半导体器件上形成高质量绝缘层的方法
公开(公告)号：US20100261355A1
公开(公告)日：2010-10-14
申请号：US12493279
申请日：2009-06-29
申请人： Sang Tae AHN , Ja Chun KU , Seung Joon JEON
发明人： Sang Tae AHN , Ja Chun KU , Seung Joon JEON
IPC分类号： H01L21/314
CPC分类号： H01L21/31608 , H01L21/02164 , H01L21/02271
摘要： A method for forming a high quality insulation layer on a semiconductor device is presented. The method includes a first step of supplying any one of a silicon source gas and an oxygen source gas into a process chamber in which a semiconductor substrate is placed; a second step of simultaneously supplying the silicon source gas and the oxygen source gas into the process chamber having undergone the first step and depositing a silicon oxide layer on the semiconductor substrate; and a third step of supplying any one of the silicon source gas and the oxygen source gas into the process chamber having undergone the second step.
摘要翻译：提出了一种在半导体器件上形成高品质绝缘层的方法。该方法包括将硅源气体和氧源气体中的任一种供给到其中放置半导体衬底的处理室中的第一步骤; 将硅源气体和氧源气体同时供给到已经经历了第一步骤的处理室中并在半导体衬底上沉积氧化硅层的第二步骤; 以及将硅源气体和氧源气体中的任一种供给到经过第二工序的处理室的第三工序。

9. 发明授权

US08736017B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08736017B2
公开(公告)日：2014-05-27
申请号：US12493594
申请日：2009-06-29
申请人： Se-Aug Jang , Hong-Seon Yang , Ja-Chun Ku , Seung-Ryong Lee
发明人： Se-Aug Jang , Hong-Seon Yang , Ja-Chun Ku , Seung-Ryong Lee
IPC分类号： H01L21/70
CPC分类号： H01L21/28008 , H01L21/823437 , H01L21/823462 , H01L21/823481 , H01L27/1052 , H01L27/10808 , H01L27/10891 , H01L27/10894 , H01L27/10897 , H01L29/4236
摘要： A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer.
摘要翻译：一种半导体器件包括：衬底，其包括沟槽，填充沟槽的一部分的掩埋栅极，形成在掩埋栅极上以间隙填充沟槽的其余部分的层间电介质层，以及覆盖基本上整个表面的保护层包括层间电介质层的基板。

10. 发明授权

US08530330B2 Method for manufacturing a semiconductor device capable of preventing the decrease of the width of an active region 有权
标题翻译：一种能够防止活性区域的宽度减小的半导体装置的制造方法
公开(公告)号：US08530330B2
公开(公告)日：2013-09-10
申请号：US12100455
申请日：2008-04-10
申请人： Sang Tae Ahn , Ja Chun Ku , Eun Jeong Kim , Wan Soo Kim
发明人： Sang Tae Ahn , Ja Chun Ku , Eun Jeong Kim , Wan Soo Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76224
摘要： A method for manufacturing a semiconductor device that can prevent the loss of an isolation structure and that can also stably form epi-silicon layers is described. The method for manufacturing a semiconductor device includes defining trenches in a semiconductor substrate having active regions and isolation regions. The trenches are partially filled with a first insulation layer. An etch protection layer is formed on the surfaces of the trenches that are filled with the first insulation layer. A second insulation layer is filled in the trenches formed with the etch protection layer to form an isolation structure in the isolation regions of the semiconductor substrate. Finally, portions of the active regions of the semiconductor substrate are recessed such that the isolation structure has a height higher than the active regions of the semiconductor substrate.
摘要翻译：描述了可以防止隔离结构的损失并且还可以稳定地形成外延硅层的半导体器件的制造方法。半导体器件的制造方法包括在具有有源区和隔离区的半导体衬底中限定沟槽。沟槽部分地填充有第一绝缘层。在填充有第一绝缘层的沟槽的表面上形成蚀刻保护层。在由蚀刻保护层形成的沟槽中填充第二绝缘层，以在半导体衬底的隔离区域中形成隔离结构。最后，半导体衬底的有源区的部分被凹入，使得隔离结构的高度高于半导体衬底的有源区。

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