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1. 发明专利

IL240717A Novel insulin analog and use thereof 未知
公开(公告)号：IL240717A
公开(公告)日：2020-05-31
申请号：IL24071715
申请日：2015-08-20
申请人： SUNG HEE HONG , DAE JIN KIM , YONG HO HUH , SUNG YOUB JUNG , SE CHANG KWON , KIM SEUNG SU , HANMI PHARM IND CO LTD , SANG YOUN HWANG , IN YOUNG CHOI , MYUNG HYUN JANG , HYUN UK KIM , JIN YOUNG KIM
发明人： SUNG HEE HONG , DAE JIN KIM , YONG HO HUH , SUNG YOUB JUNG , SE CHANG KWON , KIM SEUNG SU , SANG YOUN HWANG , IN YOUNG CHOI , MYUNG HYUN JANG , HYUN UK KIM , JIN YOUNG KIM
IPC分类号： A61K47/68 , A61K47/60
摘要： The present invention relates to an insulin analog that has a reduced insulin titer and a reduced insulin receptor binding affinity compared to the native form for the purpose of increasing the blood half-life of insulin, a conjugate prepared by linking the insulin analog and a carrier, a long-acting formulation including the conjugate, and a method for preparing the conjugate.

2. 发明专利

IL240717D0 Novel insulin analog and use thereof 未知
公开(公告)号：IL240717D0
公开(公告)日：2015-10-29
申请号：IL24071715
申请日：2015-08-20
申请人： SUNG HEE HONG , DAE JIN KIM , YONG HO HUH , SUNG YOUB JUNG , SE CHANG KWON , KIM SEUNG SU , HANMI PHARM IND CO LTD , SANG YOUN HWANG , IN YOUNG CHOI , MYUNG HYUN JANG , HYUN UK KIM , JIN YOUNG KIM
发明人： SUNG HEE HONG , DAE JIN KIM , YONG HO HUH , SUNG YOUB JUNG , SE CHANG KWON , KIM SEUNG SU , SANG YOUN HWANG , IN YOUNG CHOI , MYUNG HYUN JANG , HYUN UK KIM , JIN YOUNG KIM
IPC分类号： C07K20060101
摘要： The present invention relates to an insulin analog that has a reduced insulin titer and a reduced insulin receptor binding affinity compared to the native form for the purpose of increasing the blood half-life of insulin, a conjugate prepared by linking the insulin analog and a carrier, a long-acting formulation including the conjugate, and a method for preparing the conjugate.

3. 发明申请

US20180311580A1 TIMING DETERMINATION-TYPE GAMING DEVICE AND METHOD 审中-公开
公开(公告)号：US20180311580A1
公开(公告)日：2018-11-01
申请号：US15770180
申请日：2016-12-07
申请人： Jin Young KIM
发明人： Jin Young KIM
IPC分类号： A63F13/44 , A63F13/814
CPC分类号： A63F13/44 , A63F13/2145 , A63F13/52 , A63F13/814
摘要： Disclosed are a timing determination-type game apparatus and method. The present invention may provide a new type of timing determination-type game in which a user operates at least one timing pointer or at least one input pointer to match each other at the same position at a designated timing while moving at least one timing pointer or at least one input pointer in the unit of a group regardless of a path. Further, according to the present invention, it is possible to simultaneously move a plurality of timing pointers or a plurality of input pointers in the unit of the group without damaging timing information provided by the timing pointer and the input pointer, thereby providing various user interfaces for operating the game.

4. 发明授权

US09313314B2 Wireless network connection controlling method using device impact, application program controlling method, and devices thereof 有权
标题翻译：使用设备影响的无线网络连接控制方法，应用程序控制方法及其装置
公开(公告)号：US09313314B2
公开(公告)日：2016-04-12
申请号：US13265559
申请日：2010-03-23
申请人： Jin Young Kim , Jin Yeop Chang , Hyo Jin Yoon , Won-Il Lee , Chung Hyeok Lee
发明人： Jin Young Kim , Jin Yeop Chang , Hyo Jin Yoon , Won-Il Lee , Chung Hyeok Lee
IPC分类号： H04L12/28 , H04M1/725 , G06F1/16 , H04Q1/00 , H04L12/24
CPC分类号： H04M1/7253 , G06F1/1694 , G06F2200/1636 , H04L41/04 , H04L41/12 , H04M2250/12 , H04Q1/00
摘要： Wireless network connection control method of performing control for establishing and releasing wireless network connection with another device when impacts are applied to devices, application program control method of performing control for setting and executing application program when impacts are applied to devices, and device including wireless network connection control function and application program control function which use a device impact are disclosed. According to the present invention, provided is a wireless network connection control method of a device using a device impact, including generating a corresponding impact event when physical impact applied from the outside is sensed, transceiving a search message between devices based on a time at which the impact event occurred, searching for another device in which the impact event has occurred at the same time, and performing a predetermined protocol with a corresponding device according to a search result and establishing an inter-device wireless network connection.
摘要翻译：无线网络连接控制方法，当对设备施加影响时，执行用于建立和释放与另一设备的无线网络连接的控制，当对设备施加影响时执行用于设置和执行应用程序的控制的应用程序控制方法，以及包括无线网络公开了使用设备影响的连接控制功能和应用程序控制功能。根据本发明，提供了一种使用设备影响的设备的无线网络连接控制方法，包括当感测到从外部施加的物理冲击时产生相应的冲击事件，在设备之间基于时间来收发搜索消息发生影响事件，同时搜索影响事件发生的其他设备，并根据搜索结果与对应的设备执行预定协议，并建立设备间无线网络连接。

5. 发明授权

US08691882B2 Organic-inorganic hybrid scaffolds with surface-immobilized nano-hydroxyapatite and preparation method thereof 有权
标题翻译：具有表面固定化纳米羟基磷灰石的有机 - 无机杂化支架及其制备方法
公开(公告)号：US08691882B2
公开(公告)日：2014-04-08
申请号：US12635615
申请日：2009-12-10
申请人： Sang Cheon Lee , Jeong Ho Chang , Jin Hyung Lee , Kyung Ja Kim , Sung Eun Kim , Ho Chan Hwang , Ke-Won Kang , Seog-Jin Seo , Jin-Young Kim
发明人： Sang Cheon Lee , Jeong Ho Chang , Jin Hyung Lee , Kyung Ja Kim , Sung Eun Kim , Ho Chan Hwang , Ke-Won Kang , Seog-Jin Seo , Jin-Young Kim
IPC分类号： C07K14/78 , C08J9/00 , C08G63/06
CPC分类号： A61L27/46
摘要： Provided are an organic-inorganic hybrid scaffold with surface-immobilized nano-hydroxyapatite, and a method for the fabrication thereof. The scaffold is fabricated by reacting an acid group present on a surface of nano-hydroxyapatite with a primary amine present on a surface of a polymer support in the presence of EDC (1-ethyl-3-dimethylaminopropyl carbodiimide) to immobilize nano-hydroxyapatite onto the surface of the polymer support. The surface of nano-hydroxyapatite is previously grafted with poly(ethylene glycol methacrylate phosphate) (PolyEGMP) having phosphonic acid functionality or with a polymer having carboxylic acid functionality.
摘要翻译：提供具有表面固定的纳米羟基磷灰石的有机 - 无机杂化支架及其制造方法。在EDC（1-乙基-3-二甲基氨基丙基碳二亚胺）存在下，将存在于纳米羟基磷灰石的表面上的酸基与存在于聚合物载体表面上的伯胺反应，使纳米羟基磷灰石固定在聚合物载体的表面。预先用具有膦酸官能度的聚（乙二醇甲基丙烯酸酯磷酸酯）（PolyEGMP）或具有羧酸官能团的聚合物接枝纳米羟基磷灰石的表面。

6. 发明申请

US20130305458A1 Functional Pillow for Preventing Head Deformation of Infants Due to Posture 审中-公开
标题翻译：功能枕头防止由于姿势引起的婴儿头部变形
公开(公告)号：US20130305458A1
公开(公告)日：2013-11-21
申请号：US13982998
申请日：2011-06-08
申请人： Jin young Kim
发明人： Jin young Kim
IPC分类号： A47G9/10
CPC分类号： A47G9/10 , A61F5/05891 , A61G7/05715 , A61G13/121
摘要： The present invention relates to a functional pillow for preventing positional head deformity of an infant. The functional pillow includes an inner foam member which is porous, an outer cover which encloses the inner foam member and includes a plurality of through-holes formed thereon, a head seating portion which is formed on at least one of a top surface and a bottom surface of a pillow body which includes the inner foam member and the outer cover in an eccentric position to allow a head to be placed thereon, and at least one layered auxiliary pillow which is inserted into the head seating portion and includes an auxiliary head seating portion of a different size formed on a surface. A degree of layering of the auxiliary pillow is different according to a head size.
摘要翻译：本发明涉及一种用于防止婴儿的位置头畸形的功能性枕头。所述功能性枕头包括多孔的内部泡沫构件，封闭所述内部泡沫构件并且包括形成在其上的多个通孔的外盖，头部座部，其形成在顶部表面和底部的至少一个上枕头主体的表面，其包括内部泡沫构件和外盖，偏心位置以允许头部放置在其上;以及至少一个分层的辅助枕头，其插入到头部支座部分中，并且包括辅助头部支座部分形成在表面上的不同尺寸。辅助枕头的层次程度根据头部大小而不同。

7. 发明授权

US08586660B2 Dielectric paste composition, method of forming dielectric layer, dielectric layer, and device including the dielectric layer 有权
标题翻译：电介质浆料组合物，形成介质层的方法，介电层以及包括介电层的器件
公开(公告)号：US08586660B2
公开(公告)日：2013-11-19
申请号：US13040103
申请日：2011-03-03
申请人： Sun-jin Song , Jin-young Kim , Shang-hyeun Park , Min-jong Bae , Tae-won Jeong
发明人： Sun-jin Song , Jin-young Kim , Shang-hyeun Park , Min-jong Bae , Tae-won Jeong
IPC分类号： C08K5/20
CPC分类号： H01B3/30 , C08K5/02 , C08L5/00
摘要： A dielectric paste composition including: a plurality of inorganic dielectric particles, a binder, a solvent, and a halogenated hydrocarbon. Also disclosed is a method of forming a dielectric layer, a dielectric layer, and a device including the dielectric layer.
摘要翻译：一种电介质糊剂组合物，包括：多种无机介电颗粒，粘合剂，溶剂和卤代烃。还公开了形成电介质层，电介质层和包括电介质层的器件的方法。

8. 发明授权

US08461687B2 Semiconductor devices including bit line contact plug and buried channel array transistor, and semiconductor modules, electronic circuit boards and electronic systems including the same 有权
标题翻译：包括位线接触插头和掩埋沟道阵列晶体管的半导体器件，以及包括其的电子电路板和电子系统的半导体模块
公开(公告)号：US08461687B2
公开(公告)日：2013-06-11
申请号：US13072907
申请日：2011-03-28
申请人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
发明人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
IPC分类号： H01L29/40 , H01L29/66
CPC分类号： H01L23/528 , H01L23/535 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L29/0649 , H01L29/42324 , H01L29/45 , H01L29/78 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
摘要翻译：具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管和周边晶体管上电极。位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。

9. 发明授权

US08363482B2 Flash memory devices with selective bit line discharge paths and methods of operating the same 有权
标题翻译：具有选择性位线放电路径的闪存器件及其操作方法
公开(公告)号：US08363482B2
公开(公告)日：2013-01-29
申请号：US12813050
申请日：2010-06-10
申请人： Euido Kim , BongYong Lee , Haebum Lee , Sang-Youl Kwon , Jin-Young Kim , Hye Yeon Yun , Houng-kuk Jang
发明人： Euido Kim , BongYong Lee , Haebum Lee , Sang-Youl Kwon , Jin-Young Kim , Hye Yeon Yun , Houng-kuk Jang
IPC分类号： G11C11/34
CPC分类号： G11C16/06
摘要： Provided is a flash memory device that can include a memory cell configured to store data, a local bit line that is connected to the memory cell, a global bit line that is connected to the local bit line, a discharge transistor that is connected to the global bit line, and that is configured to selectively connect the global bit line to a reference level responsive to a discharge control signal, and a discharge control circuit, that is connected to the discharge transistor via the discharge control signal, and that is configured to selectively disable the discharge transistor during an erase interval occurring before a verify interval of an erase verification operation carried out by the flash memory device.
摘要翻译：提供了一种闪存器件，其可以包括被配置为存储数据的存储器单元，连接到存储单元的局部位线，连接到本地位线的全局位线，连接到本地位线的放电晶体管全局位线，并且被配置为响应于放电控制信号选择性地将全局位线连接到参考电平;以及放电控制电路，其通过放电控制信号连接到放电晶体管，并且被配置为在由闪速存储器件执行的擦除验证操作的验证间隔之前的擦除间隔期间，选择性地禁用放电晶体管。

10. 发明授权

US08331162B2 Semiconductor memory device having hierarchical bit line structure and method of driving the semiconductor memory device 失效
标题翻译：具有分级位线结构的半导体存储器件和驱动半导体存储器件的方法
公开(公告)号：US08331162B2
公开(公告)日：2012-12-11
申请号：US12662222
申请日：2010-04-06
申请人： Jin-young Kim , Ki-whan Song
发明人： Jin-young Kim , Ki-whan Song
IPC分类号： G11C7/10
CPC分类号： G11C7/18 , G11C7/12 , G11C11/4094 , G11C11/4097
摘要： The semiconductor memory device includes a first memory cell array including at least one first memory cell and at least one second memory cell corresponding to the at least one first memory cell, a first low bit line connected to the at least one first memory cell, a first low complementary bit line connected to the at least one second memory cell, a first switch unit having a first terminal connected to the first low bit line, a second switch unit having a first terminal connected to the first low complementary bit line, a first global bit line connected to a second terminal of the first switch unit, a first global complementary bit line connected to a second terminal of the second switch unit, and a plurality of sensing amplifying units connected to the first global bit line and the first global complementary bit line.
摘要翻译：半导体存储器件包括第一存储器单元阵列，其包括至少一个第一存储单元和与该至少一个第一存储单元对应的至少一个第二存储单元，连接至该至少一个第一存储单元的第一低位线，连接到所述至少一个第二存储器单元的第一低互补位线，具有连接到所述第一低位线的第一端子的第一开关单元，具有连接到所述第一低互补位线的第一端子的第二开关单元，连接到第一开关单元的第二端子的全局位线，连接到第二开关单元的第二端子的第一全局互补位线以及连接到第一全局位线和第一全局互补位置的多个感测放大单元位线。

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