专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20040021166A1 Pseudo-nonvolatile direct-tunneling floating-gate device 审中-公开
标题翻译：伪非易失性直接隧道浮栅器件
公开(公告)号：US20040021166A1
公开(公告)日：2004-02-05
申请号：US10356645
申请日：2003-01-31
申请人： Impinj, Inc., a Delaware Corporation
发明人： John D. Hyde , Todd E. Humes , Christopher J. Diorio , Carver A. Mead
IPC分类号： H01L029/76
CPC分类号： H01L27/11521 , H01L27/11519 , H01L27/11558 , H01L29/7883
摘要： A semiconductor device is provided that uses a floating gate to store analog- and digital-valued information for periods of time measured in milliseconds to hours. Charge is added to and/or removed from the floating gate by means of direct electron tunneling through the surrounding insulator, with the insulator typically being thin enough such that appreciable tunneling occurs with an insulator voltage smaller than the difference in electron affinities between the semiconductor and the insulator and/or between the floating gate and the insulator. The stored information is refreshed or updated as needed. In many applications, the stored information can be refreshed without interrupting normal circuit operation. Adding and removing charge to or from the floating gate may be performed using separate circuit inputs, to tailor the performance and response of the floating-gate device. There is no need to use a control gate in the floating-gate structures disclosed herein.
摘要翻译：提供了一种半导体器件，其使用浮动栅极来存储以毫秒到数小时为单位的时间段的模拟和数字值信息。通过直接电子隧道穿过周围的绝缘体将电荷添加到浮动栅极和/或从浮动栅极去除，绝缘体通常足够薄，使得明显的隧道发生，其绝缘体电压小于半导体和绝缘体和/或浮动栅极和绝缘体之间。存储的信息根据需要刷新或更新。在许多应用中，存储的信息可以刷新而不中断正常的电路操作。可以使用单独的电路输入来对浮动栅极添加和去除电荷或从浮动栅极去除电荷，以调整浮动栅极器件的性能和响应。在本文公开的浮动栅极结构中不需要使用控制栅极。

2. 发明申请

US20040206999A1 Metal dielectric semiconductor floating gate variable capacitor 审中-公开
标题翻译：金属介质半导体浮栅可变电容器
公开(公告)号：US20040206999A1
公开(公告)日：2004-10-21
申请号：US10143557
申请日：2002-05-09
申请人： Impinj, Inc., a Delaware Corporation
发明人： John D. Hyde , Yanjun Ma
IPC分类号： H01L021/8242 , H01L027/108 , H01L029/76 , H01L031/119 , H01L029/00 , H01L021/20
CPC分类号： H01L27/11521 , H01L27/11519 , H01L27/11558 , H01L29/7883
摘要： A simple metal dielectric semiconductor (MDS) variable capacitor which may be a MOS capacitor uses the drain and source of a floating gate metal dielectric semiconductor field effect transistor connected to the bulk of the semiconductor substrate as one plate of the capacitor and the gate of the transistor as the other plate. The capacitance is voltage dependent and is strongly nonlinear in the depletion region. The accumulation and strong inversion regions are also nonlinear, but to a much smaller degree. The nonlinearity can be significantly reduced by connecting two of the capacitors in series. This series connection also makes possible a capacitor structure with an isolated floating gate connecting the two series capacitors. The charge on the floating gate can be controlled by tunneling and injection to vary the capacitor bias voltage and thus, its capacitance. Alternatively, the capacitors may operate in the accumulation region. In this configuration the accumulation capacitors do not require transistors nor do they require source and drain regions. The capacitance appears between the floating gate and the bulk (well). In other respects they operate as described above.
摘要翻译：可以是MOS电容器的简单金属介电半导体（MDS）可变电容器使用连接到半导体衬底的主体的浮栅金属介电半导体场效应晶体管的漏极和源极作为电容器的一个栅极和晶体管作为另一块板。电容是电压依赖性的，在耗尽区域是强非线性的。积累和强反演区域也是非线性的，但程度要小得多。通过串联两个电容器可以显着降低非线性。该串联连接也使得可能的电容器结构具有连接两个串联电容器的隔离的浮动栅极。浮动栅极上的电荷可以通过隧道和注入来控制，以改变电容器偏置电压，从而改变其电容。或者，电容器可以在累积区域中操作。在这种配置中，积累电容器不需要晶体管，也不需要源极和漏极区域。电容出现在浮动栅极和体积（阱）之间。在其他方面，它们如上所述地操作。

3. 发明申请

US20040124892A1 Use of analog-valued floating-gate transistors to match the electrical characteristics of interleaved and pipelined circuits 有权
标题翻译：使用模拟值浮栅晶体管来匹配交错和流水线电路的电气特性
公开(公告)号：US20040124892A1
公开(公告)日：2004-07-01
申请号：US10681577
申请日：2003-10-07
申请人： Impinj, Inc., a Delaware Corporation
发明人： Christopher J. Diorio , Todd E. Humes , Michael Thomas
IPC分类号： H03B001/00
CPC分类号： G06F1/10 , G11C27/005 , G11C27/024 , H03K5/135 , H03K5/1502 , H03K5/2481 , H03K5/249 , H03K2005/00026 , H03K2005/00058 , H03K2005/00084 , H03M1/0602 , H03M1/1215 , H03M1/164 , H03M1/442
摘要： Methods of and apparatuses for matching the signal delay, clock timing, frequency response, gain, offset, and/or transfer function of signal pathways in electrical circuits such as, for example, time-interleaved and pipelined circuits using analog-valued floating-gate MOSFETs are disclosed. The methods and apparatuses disclosed are applicable to a variety of circuits, including but not limited to, sample-and-hold or track-and-hold circuits, quadrature mixers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), analog or digital filters, and amplifiers.
摘要翻译：用于使电路中的信号路径的信号延迟，时钟定时，频率响应，增益，偏移和/或传递函数匹配的方法和设备，例如使用模拟值浮动栅极的时间交织和流水线电路公开了MOSFET。所公开的方法和装置适用于各种电路，包括但不限于采样保持或跟踪保持电路，正交混频器，模数转换器（ADC），数模转换器转换器（DAC），模拟或数字滤波器和放大器。

4. 发明申请

US20040052113A1 Method and apparatus for preventing overtunneling in pFET-based nonvolatile memory cells 有权
标题翻译：用于防止基于pFET的非易失性存储单元中的过度隧穿的方法和装置
公开(公告)号：US20040052113A1
公开(公告)日：2004-03-18
申请号：US10245183
申请日：2002-09-16
申请人： Impinj, Inc., a Delaware Corporation
发明人： Christopher J. Diorio , Chad Lindhorst , Shail Srinivas , Alberto Pesavento , Troy Gilliland
IPC分类号： G11C016/04 , G11C011/34
CPC分类号： G11C16/3477 , G11C16/3404 , G11C16/3468 , G11C16/3472
摘要： Methods and apparatuses prevent overtunneling in pFET-based nonvolatile floating gate memory (NVM) cells. During a tunneling process, in which charge carriers are removed from a floating gate of a pFET-based NVM cell, a channel current of a memory cell transistor is monitored and compared to a predetermined minimum channel current required to maintain a conducting channel in an injection transistor of the memory cell. When the monitored channel current drops below the predetermined minimum channel current, charge carriers are injected onto the floating gate by impact-ionized hot-electron injection (IHEI) so that overtunneling is avoided.
摘要翻译：方法和装置可以防止基于pFET的非易失性浮动栅极存储器（NVM）单元中的超导。在其中从基于pFET的NVM单元的浮置栅极去除电荷载流子的隧穿过程中，监测存储单元晶体管的沟道电流，并将其与在注入中维持导通通道所需的预定最小沟道电流进行比较晶体管的存储单元。当监测的通道电流下降到预定的最小通道电流以下时，电荷载流子通过冲击电离热电子注入（IHEI）注入到浮动栅极上，从而避免了超导。

5. 发明申请

US20040195593A1 Counteracting overtunneling in nonvolatile memory cells 有权
标题翻译：在非易失性存储单元中反作用超导
公开(公告)号：US20040195593A1
公开(公告)日：2004-10-07
申请号：US10830280
申请日：2004-04-21
申请人： Impinj, Inc., a Delaware Corporation
发明人： Christopher J. Diorio , Chad A. Lindhorst , Shailendra Srinivas , Alberto Pesavento , Troy N. Gilliland
IPC分类号： H01L027/10
CPC分类号： G11C16/3468 , G11C16/3404 , G11C16/3472 , G11C16/3477 , G11C16/3486 , G11C2216/10
摘要： Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.
摘要翻译：方法和装置防止非易失性浮动栅极存储器（NVM）单元中的超导。单个电池包括具有晶体管的电路，其具有存储电荷的浮动栅极，以及用于从栅极提取电荷的电容器结构，例如通过隧穿。反作用电路防止从浮动栅极提取电荷超过阈值，因此防止对其进行过度隧穿或纠正。在一个实施例中，反作用电路将电子提供给浮动栅极，以补偿超出点的隧穿。在另一个实施例中，抵消电路包括开关和当达到适当的阈值时触发开关的传感器。开关可以以任何数量的适当方式布置，例如防止高电压施加到电容器结构，或者防止电源施加到晶体管的端子或晶体管的阱。

6. 发明申请

US20040037127A1 Differential floating gate nonvolatile memories 有权
标题翻译：差分浮栅非易失性存储器
公开(公告)号：US20040037127A1
公开(公告)日：2004-02-26
申请号：US10437262
申请日：2003-05-12
申请人： Impinj, Inc., A Delaware Corporation
发明人： Chad A. Lindhorst , Christopher J. Diorio , Troy N. Gilliland , Alberto Pesavento , Shail Srinivas , Yanjun Ma , Terry Hass , Kambiz Rahimi
IPC分类号： G11C007/00
CPC分类号： G11C16/0441 , G11C16/28 , G11C16/3468 , G11C16/3486 , G11C2216/10
摘要： A number of designs for differential floating gate nonvolatile memories and memory arrays utilize differential pFET floating gate transistors to store information. Methods of implementing such memories and memory arrays together with methods of operation and test associated with such memories and memory arrays are presented.
摘要翻译：用于差分浮置非易失性存储器和存储器阵列的许多设计利用差分pFET浮栅晶体管来存储信息。提出了实现这种存储器和存储器阵列的方法以及与这种存储器和存储器阵列相关联的操作和测试方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式