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1. 发明申请

US20040266126A1 Method for manufacturing semiconductor capacitor having double dielectric layer therein 有权
标题翻译：制造其中具有双电介质层的半导体电容器的方法
公开(公告)号：US20040266126A1
公开(公告)日：2004-12-30
申请号：US10738177
申请日：2003-12-16
发明人： Kee-Jeung Lee
IPC分类号： H01L021/20 , H01L021/8242
CPC分类号： H01L28/65 , H01L27/10817 , H01L28/75
摘要： The method for manufacturing a DRAM capacitor is employed to enhance charge capacitance and electrical endurance of the DRAM capacitor by structuring a double dielectric layer of aluminum oxide (Al2O3) and hafnium oxide (HfO2). The method includes steps of: preparing an active matrix including a semiconductor substrate, an ILD formed on the semiconductor substrate and a storage node obtained after patterning the ILD into a predetermined configuration; forming a bottom electrode on top faces of the storage node and portions of the ILD; forming a diffusion barrier on an exposed surface of the bottom electrode; forming a double dielectric layer including an aluminum oxide layer and a hafnium oxide layer, wherein the aluminum oxide layer and the hafnium oxide layer are formed on the diffusion barrier in succession; carrying out an annealing process for recovering dielectric properties of the aluminum oxide layer and the hafnium oxide layer; and forming a top electrode on the hafnium oxide layer.

2. 发明申请

US20040266099A1 Integrated circuit, its fabrication process and memory cell incorporating such a circuit 有权
标题翻译：集成电路，其制造工艺和包含这种电路的存储单元
公开(公告)号：US20040266099A1
公开(公告)日：2004-12-30
申请号：US10486950
申请日：2004-08-20
发明人： Catherine Mallardeau , Pascale Mazoyer , Marc Piazza
IPC分类号： H01L021/8242 , H01L027/108 , H01L029/76 , H01L029/94 , H01L031/119
CPC分类号： H01L27/10894 , H01L27/10852 , H01L28/91
摘要： This integrated circuit comprises a capacitor (23) formed above a substrate (1) inside a first cavity in a dielectric and comprising a first electrode, a second electrode, a thin dielectric layer placed between the two electrodes, and a structure (7) for connection to the capacitor. The connection structure is formed at the same level as the capacitor in a second cavity narrower than the first cavity, the said second cavity being completely filled by an extension of at least one of the electrodes of the capacitor.
摘要翻译：该集成电路包括形成在电介质的第一空腔内部的衬底（1）上方的电容器（23），其包括第一电极，第二电极，设置在两个电极之间的薄介电层，以及用于连接到电容器。连接结构形成在与第一空腔更窄的第二空腔中的电容器相同的水平处，所述第二空腔由电容器的至少一个电极的延伸部完全填充。

3. 发明申请

US20040266095A1 Method for manufacturing ferroelectric random access memory capacitor 有权
标题翻译：铁电随机存取存储器电容器的制造方法
公开(公告)号：US20040266095A1
公开(公告)日：2004-12-30
申请号：US10731357
申请日：2003-12-08
发明人： Sang-Hyun Oh , Young-Ho Yang , Kye-Nam Lee , Suk-Kyoung Hong
IPC分类号： H01L021/8242 , H01L021/00
CPC分类号： H01L27/11507 , H01L21/31053 , H01L21/76801 , H01L27/11502 , H01L28/55 , H01L28/65 , H01L28/75
摘要： A method for manufacturing an FeRAM capacitor is employed to enhance an adhesive property between a dielectric layer and a first bottom electrode of iridium. The method including the steps of: preparing an active matrix including a semiconductor substrate, a transistor, a bit line, a first ILD, a second ILD and a storage node; forming a first bottom electrode on the second ILD and the storage node; forming a third ILD on exposed surfaces of the first bottom electrode and the second ILD; planarizing the third ILD till a top face of the first bottom electrode is exposed; forming a second bottom electrode on the top face of the bottom electrode; forming conductive oxides on exposed sidewalls of the first bottom electrode by carrying out an oxidation process; forming a dielectric layer on exposed surfaces of the first bottom electrodes, the second bottom electrode and the second ILD; and forming a top electrode on the dielectric layer.

4. 发明申请

US20040266032A1 Method for fabricating ferroelectric random access memory device with merged-top electrode-plateline capacitor 有权
标题翻译：具有合并顶电极 - 平板电容器的铁电随机存取存储器件的制造方法
公开(公告)号：US20040266032A1
公开(公告)日：2004-12-30
申请号：US10741670
申请日：2003-12-18
发明人： Sang-Hyun Oh , Kyu-Hyun Bang , In-Woo Jang , Jin-Yong Seong , Jin-Gu Kim , Song-Hee Park , Young-Ho Yang , Kye-Nam Lee , Suk-Kyoung Hong
IPC分类号： H01L021/00 , H01L021/8242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/57
摘要： The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM) device. The method includes the steps of: forming a first inter-layer insulation layer on a substrate; forming a storage node contact connected with a partial portion of the substrate by passing through the first inter-layer insulation layer; forming a lower electrode connected to the storage node contact on the first inter-layer insulation layer; forming a second inter-layer insulation layer having a surface level lower than that of the lower electrode so that the second inter-layer insulation layer encompasses a bottom part of the lower electrode; forming an impurity diffusion barrier layer encompassing an upper part of the lower electrode on the second inter-layer insulation layer; forming a ferroelectric layer on the lower electrode and the impurity diffusion barrier layer; and forming a top electrode on the ferroelectric layer.
摘要翻译：本发明涉及一种制造铁电随机存取存储器（FeRAM）器件的方法。该方法包括以下步骤：在衬底上形成第一层间绝缘层; 通过穿过所述第一层间绝缘层形成与所述基板的部分部分连接的存储节点接触件; 在所述第一层间绝缘层上形成连接到所述存储节点接点的下电极; 形成具有低于下电极的表面电平的第二层间绝缘层，使得第二层间绝缘层包围下电极的底部; 在所述第二层间绝缘层上形成包围所述下电极的上部的杂质扩散阻挡层; 在下电极和杂质扩散阻挡层上形成铁电层; 以及在所述铁电层上形成顶部电极。

5. 发明申请

US20040256653A1 Semiconductor device and manufacturing method therefor, portable electronic equipment, and IC card 有权
标题翻译：半导体装置及其制造方法，便携式电子设备和IC卡
公开(公告)号：US20040256653A1
公开(公告)日：2004-12-23
申请号：US10842424
申请日：2004-05-11
发明人： Hiroshi Iwata , Takayuki Ogura , Akihide Shibata
IPC分类号： H01L029/768 , H01L021/8242
CPC分类号： H01L27/11568 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L27/105 , H01L27/115 , H01L27/11502 , H01L27/11521 , H01L27/11534 , H01L27/1159 , H01L27/1463 , H01L29/7923
摘要： A semiconductor switching element and a semiconductor storage element each have a gate electrode, a pair of source/drain regions and a channel forming region. Memory function bodies having a function of storing electric charges are provided on opposite sides of the gate electrode of the semiconductor storage element. In the semiconductor storage element, an amount of current that flows from one of the source/drain regions to the other of the source/drain regions upon application of a voltage to the gate electrode is variable depending on an amount of electric charges retained in the memory function body.
摘要翻译：半导体开关元件和半导体存储元件各自具有栅极电极，一对源极/漏极区域和沟道形成区域。具有存储电荷功能的记忆功能体设置在半导体存储元件的栅电极的相对侧上。在半导体存储元件中，在向栅电极施加电压时，从源极/漏极区域中的一个流到源极/漏极区域中的一个的电流量根据保持在栅极电极中的电荷量而变化记忆功能体。

6. 发明申请

US20040248364A1 Method of forming a memory cell with a single sided buried strap 有权
标题翻译：用单面埋置带形成存储单元的方法
公开(公告)号：US20040248364A1
公开(公告)日：2004-12-09
申请号：US10722647
申请日：2003-11-26
申请人： Nanya Technology Corporation
发明人： Chih-Yuan Hsiao , Yi-Nan Chen
IPC分类号： H01L021/8242 , H01L021/20
CPC分类号： H01L27/10867 , H01L27/10864
摘要： A method of forming a memory cell with a single sided buried strap. A collar oxide layer is formed on the sidewall of a trench. A conductive layer fills the trench. The conductive layer and the collar oxide layer are partially removed to form an opening having first and second sidewalls. The remaining collar oxide layer is lower than the remaining conductive layer. An angle implantation with F ions is performed on the first sidewall. A thermal oxidation process is performed to form a first oxide layer on the first sidewall and a second oxide layer on the second sidewall. The first oxide layer is thicker than the second oxide layer. The second oxide layer is removed to expose the second sidewall. A buried strap is formed at the bottom of the opening, insulated from the first sidewall by the first oxide layer.
摘要翻译：一种用单面埋置带形成存储单元的方法。环状氧化物层形成在沟槽的侧壁上。导电层填充沟槽。导电层和套环氧化物层被部分去除以形成具有第一和第二侧壁的开口。剩余的环状氧化物层比剩余的导电层低。在第一侧壁上进行具有F离子的角度注入。进行热氧化处理以在第一侧壁上形成第一氧化物层，在第二侧壁上形成第二氧化物层。第一氧化物层比第二氧化物层厚。去除第二氧化物层以暴露第二侧壁。在开口的底部形成掩埋带，通过第一氧化物层与第一侧壁绝缘。

7. 发明申请

US20040248362A1 Semiconductor device and fabrication method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20040248362A1
公开(公告)日：2004-12-09
申请号：US10777704
申请日：2004-02-13
申请人： ELPIDA MEMORY, INC. , Hitachi ULSI Systems, Co., Ltd. , HITACHI LTD.
发明人： Yoshitaka Nakamura , Hidekazu Goto , Isamu Asano , Mitsuhiro Horikawa , Keiji Kuroki , Hiroshi Sakuma , Kenichi Koyanagi , Tsuyoshi Kawagoe
IPC分类号： H01L021/8242 , H01L029/76
CPC分类号： H01L28/65 , H01L21/7687 , H01L27/10814 , H01L27/10852
摘要： A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.
摘要翻译：一种半导体器件包括各自具有形成在半导体衬底的一个主表面上的用于存储器选择的MISFET的存储单元，以及由用于存储器选择的MISFET的源极和漏极的底部电连接到下部电极的电容元件经由电容绝缘膜经由形成在下电极上的第一金属层和上电极。下部电极的底部的厚度为30nm以上。具有高电离比和高方向性的溅射（例如PCM）适于形成下电极，以使电容器的底部仅较厚。

8. 发明申请

US20040235241A1 Method of manufacturing semiconductor device having capacitor 审中-公开
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US20040235241A1
公开(公告)日：2004-11-25
申请号：US10793867
申请日：2004-03-08
申请人： Renesas Technology Corp.
发明人： Masatoshi Anma , Masahiko Takeuchi
IPC分类号： H01L021/8242
CPC分类号： H01L28/91 , H01L21/31683 , H01L27/10852 , H01L28/65
摘要： It is an object to obtain a method of manufacturing a semiconductor device having a capacitor capable of avoiding generation of a leakage current and an electrical short circuit between electrodes which are caused by a sharp portion of a lower electrode of the capacitor and a deterioration in a crystallinity of a dielectric film of the capacitor which is caused by a residue. A surface of a ruthenium film (7) is oxidized by a low temperature plasma oxidation process to form a ruthenium oxide film (9). Also in the case in which a part of a residue (51) exists on the surface of the ruthenium film (7), the existing residue (51) is lifted off and disappears by formation of the ruthenium oxide film (9) containing RuO4 having a high vapor pressure in a large amount. The low temperature plasma oxidation process, moreover, has an anisotropy an oxidation rate in a vertical direction is higher than that in a transverse direction. Accordingly, an upper end of a side wall portion of the ruthenium film (7) is greatly oxidized in the vertical direction and is thus rounded. As a result, a sharp portion (50) disappears.
摘要翻译：本发明的目的是获得一种具有电容器的半导体器件的制造方法，所述电容器能够避免由电容器的下部电极的尖锐部分引起的漏电流和电极之间的电短路以及电容器的劣化由残留物引起的电容器的电介质膜的结晶度。钌膜（7）的表面通过低温等离子体氧化法氧化，形成氧化钌膜（9）。此外，在钌膜（7）的表面存在一部分残留物（51）的情况下，通过形成含有RuO 4的氧化钌膜（9），使现有的残渣（51）脱落而消失，所述RuO 4具有大量蒸气压高。此外，低温等离子体氧化法具有各向异性，垂直方向的氧化速度高于横向的氧化速度。因此，钌膜（7）的侧壁部的上端在垂直方向上被大大氧化，因此是圆形的。结果，尖锐部分（50）消失。

9. 发明申请

US20040232520A1 High-density metal capacitor using dual-damascene copper interconnect 有权
标题翻译：高密度金属电容器采用双镶嵌铜互连
公开(公告)号：US20040232520A1
公开(公告)日：2004-11-25
申请号：US10869671
申请日：2004-06-16
发明人： Liming Tsau
IPC分类号： H01L021/8242
CPC分类号： H01L21/76807 , H01L23/5223 , H01L23/5252 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process, and electrically coupled with the first conductive layer, the etch-stop layer having a preselected dielectric constant and a predetermined geometry; and a second conductive layer, electrically coupled with the etch-stop layer. The structure can be, for example, a metal-insulator-metal capacitor, an antifuse, and the like.
摘要翻译：一种具有由双镶嵌制造工艺提供的第一导电层的电子结构; 由所述制造工艺提供的蚀刻停止层，并且与所述第一导电层电耦合，所述蚀刻停止层具有预选的介电常数和预定几何形状; 以及与所述蚀刻停止层电耦合的第二导电层。该结构可以是例如金属 - 绝缘体 - 金属电容器，反熔丝等。

10. 发明申请

US20040228067A1 Capacitor arrangement for obtaining increased capacitance, and method for fabricating the same 有权
标题翻译：用于获得增加的电容的电容器装置及其制造方法
公开(公告)号：US20040228067A1
公开(公告)日：2004-11-18
申请号：US10787934
申请日：2004-02-27
发明人： Martin Gutsche , Harald Seidl
IPC分类号： H01G004/228 , H01L021/8242
CPC分类号： H01L29/66181 , H01L29/945
摘要： Arrangement of capacitors which, without taking up an additional area in the semiconductor substrate, have an increased capacitance compared with conventional capacitors in DRAM memory cells. The arrangement of capacitors according to the invention is based on a combination of two or more separately arranged individual capacitors in or on a substrate to form two or more capacitors arranged one in the other or one above the other. In this case, an outer capacitor encloses at least one or a plurality of inner. capacitors or a substantial part of an upper capacitor lies above a lower capacitor. A method for fabricating the arrangement of capacitors also is described.
摘要翻译：与DRAM存储单元中的常规电容器相比，不占据半导体衬底中的附加区域的电容器的布置具有增加的电容。根据本发明的电容器的布置基于在衬底中或衬底上的两个或更多个单独布置的单独电容器的组合，以形成一个或另一个彼此排列的两个或更多个电容器。在这种情况下，外部电容器包围至少一个或多个内部。电容器或大部分上部电容器位于较低电容器的上方。还描述了制造电容器布置的方法。

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