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    • 4. 发明申请
    • METHOD FOR MANUFACTURING A MICROMACHINED DEVICE
    • 制造微型设备的方法
    • WO2008053008A3
    • 2008-06-19
    • PCT/EP2007061731
    • 2007-10-31
    • IMEC INTER UNI MICRO ELECTRASML NETHERLANDS BVWITVROUW ANNHASPESLAGH LUC
    • WITVROUW ANNHASPESLAGH LUC
    • B81C1/00
    • H01L21/324B81C1/00246B81C2203/0735Y10T428/24612
    • The present invention provides a method for manufacturing micromachined devices on a substrate (10) comprising electrical circuitry, the micromachined devices comprising at least one micromachined structure, without affecting the underlying electrical circuitry. The method comprises providing a protection layer (15) on the substrate (10); providing on the protection layer (15) a plurality of patterned layers for forming the at least one micromachined structure, the plurality of patterned layers comprising at least one sacrificial layer (18); and thereafter removing at least a portion of the sacrificial layer (18) to release the at least one micromachined structure. The method furthermore comprises, before providing the protection layer (15), annealing the substrate (10) at a temperature higher than a highest temperature used during manufacturing of the micromachined device, annealing being for preventing gas formation underneath the protection layer (15) during subsequent manufacturing steps. The present invention also provides a micromachined device obtained by the method according to embodiments of the present invention.
    • 本发明提供了一种用于在包括电路的衬底(10)上制造微加工器件的方法,所述微加工器件包括至少一个微加工结构,而不影响下面的电路。 该方法包括在衬底(10)上提供保护层(15); 在所述保护层(15)上设置多个用于形成所述至少一个微机械加工结构的图案化层,所述多个图案化层包括至少一个牺牲层(18); 然后去除所述牺牲层(18)的至少一部分以释放所述至少一个微加工结构。 该方法还包括在提供保护层(15)之前,在高于在微加工装置的制造期间使用的最高温度的温度下对衬底(10)退火,用于在保护层(15)的下方防止形成气体的退火 后续制造步骤。 本发明还提供了通过根据本发明的实施例的方法获得的微加工装置。
    • 9. 发明申请
    • COST-AWARE DESIGN-TIME/RUN-TIME MEMORY MANAGEMENT METHODS AND APPARATUS
    • COST-AWARE设计时间/运行时记忆管理方法和设备
    • WO2004046921A3
    • 2005-05-06
    • PCT/BE0300202
    • 2003-11-18
    • IMEC INTER UNI MICRO ELECTRMARCHAL PAULGOMEZ JOSE IGNACIOBRUNI DAVIDECATTHOOR FRANCKY
    • MARCHAL PAULGOMEZ JOSE IGNACIOBRUNI DAVIDECATTHOOR FRANCKY
    • G06F9/45
    • G06F8/4432G06F8/4442Y02D10/41
    • Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g. multi-banked memories in an essentially digital system as well as methods, apparatus and software products for runtime memory management techniques of such a such a system. Memory assignment techniques are described for assigning data to a hierarchical memory particularly for multi-tasked applications where data of dynamically crated/deleted tasks is allocated at run-time. The energy consumption of hierarchical memories such as multi-banked memories depends largely on how data is assigned to the memory banks. Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g. multi-banked memories in an essentially digital system which improve a cost function such as energy consumption.
    • 描述了分层存储器的设计时数据分配技术的方法,装置和软件产品,例如。 基本数字系统中的多存储存储器以及用于这种系统的运行时存储器管理技术的方法,装置和软件产品。 描述了用于将数据分配给分层存储器的内存分配技术,特别是对于在运行时分配动态封装/删除任务的数据的多任务应用程序。 分层存储器(诸如多存储器存储器)的能量消耗在很大程度上取决于数据如何被分配给存储器组。 描述了分层存储器的设计时数据分配技术的方法,装置和软件产品,例如。 在本质上数字系统中的多存储器,其改善诸如能量消耗的成本功能。
    • 10. 发明申请
    • AN ASIP ARCHITECTURE FOR DECODING AT LEAST TWO DECODING METHODS
    • 用于解码至少两种解码方法的ASIP体系结构
    • WO2009043918A3
    • 2009-08-27
    • PCT/EP2008063259
    • 2008-10-02
    • IMEC INTER UNI MICRO ELECTRPRIEWASSER ROBERTBOUGARD BRUNONAESSENS FREDERIK
    • PRIEWASSER ROBERTBOUGARD BRUNONAESSENS FREDERIK
    • H03M13/11H03M13/29
    • H03M13/1105H03M13/2775H03M13/296H03M13/6508H03M13/6513H03M13/6569H03M13/6577
    • The present invention provides a system for execution of a decoding method, the system being capable of executing at least two data decoding methods which are different in underlying coding principle, whereby at least one of said data decoding methods requires data shuffling operations on said data. A system according to embodiments of the present invention comprises: - at least one application specific processor having an instruction set comprising arithmetic operators excluding multiplication, division and power, the processor being selected for execution of approximations of each of said at least two data decoding methods, - at least a first memory unit, e.g. background memory, for storing data, - a transfer means for transferring data from the first memory unit towards said at least one programmable processor, said transfer means including a data shuffler, and - a controller for controlling the data shuffler independent from the processor.
    • 本发明提供了一种用于执行解码方法的系统,该系统能够执行至少两种不同于底层编码原理的数据解码方法,由此至少一种所述数据解码方法需要对所述数据进行数据混洗操作。 根据本发明实施例的系统包括:至少一个应用专用处理器,其具有包括除乘法,除法和功率之外的算术运算符的指令集,处理器被选择用于执行所述至少两个数据解码方法中的每一个的近似值 - 至少第一存储器单元,例如, 后台存储器,用于存储数据;传送装置,用于将数据从第一存储器单元传送到所述至少一个可编程处理器,所述传送装置包括数据混洗器;以及控制器,用于独立于处理器来控制数据混洗器。