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1. 发明申请

WO2005078690A3 POWER OPTIMISED DISPLAY ARCHITECTURE AND DRIVING METHOD 审中-公开
标题翻译：功率优化显示架构和驱动方法
公开(公告)号：WO2005078690A3
公开(公告)日：2005-10-06
申请号：PCT/BE2005000021
申请日：2005-02-14
申请人： IMEC INTER UNI MICRO ELECTR , CATTHOOR FRANCKY , DEWILDE ANDY , HOLLEVOET LIEVEN
发明人： CATTHOOR FRANCKY , DEWILDE ANDY , HOLLEVOET LIEVEN
IPC分类号： G06F3/14 , G09G5/36 , G09G5/39
CPC分类号： G06F3/14 , G09G5/363 , G09G5/39 , G09G2300/08 , G09G2310/04
摘要： The invention relates to a display system for displaying information and a method for displaying. The system comprises a processing means and a display unit with a display panel. On the image data processing path for transferring information to the display panel the number of writable memory components external to the display panel is limited to maximally one. The maximally one writable memory component is adapted to comprise at least a single image frame. The systems and methods allow to reduce the power consumption based on reduction of the number of memory accesses. Furthermore, a method and system is provided wherein updating of pixel information is performed content dependent. Moreover, a system is provided wherein the display panel is connected to the processing means using a separate, dedicated display bus.
摘要翻译：本发明涉及一种用于显示信息的显示系统和一种显示方法。该系统包括处理装置和具有显示面板的显示单元。在用于将信息传送到显示面板的图像数据处理路径上，显示面板外部的可写入存储器组件的数量被限制为最大一个。最大可写存储器组件适于包括至少单个图像帧。系统和方法允许基于减少存储器访问次数来降低功耗。此外，提供了一种方法和系统，其中像素信息的更新是依赖于内容。此外，提供了一种系统，其中显示面板使用单独的专用显示总线连接到处理装置。

2. 发明申请

WO2004046921A3 COST-AWARE DESIGN-TIME/RUN-TIME MEMORY MANAGEMENT METHODS AND APPARATUS 审中-公开
标题翻译： COST-AWARE设计时间/运行时记忆管理方法和设备
公开(公告)号：WO2004046921A3
公开(公告)日：2005-05-06
申请号：PCT/BE0300202
申请日：2003-11-18
申请人： IMEC INTER UNI MICRO ELECTR , MARCHAL PAUL , GOMEZ JOSE IGNACIO , BRUNI DAVIDE , CATTHOOR FRANCKY
发明人： MARCHAL PAUL , GOMEZ JOSE IGNACIO , BRUNI DAVIDE , CATTHOOR FRANCKY
IPC分类号： G06F9/45
CPC分类号： G06F8/4432 , G06F8/4442 , Y02D10/41
摘要： Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g. multi-banked memories in an essentially digital system as well as methods, apparatus and software products for runtime memory management techniques of such a such a system. Memory assignment techniques are described for assigning data to a hierarchical memory particularly for multi-tasked applications where data of dynamically crated/deleted tasks is allocated at run-time. The energy consumption of hierarchical memories such as multi-banked memories depends largely on how data is assigned to the memory banks. Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g. multi-banked memories in an essentially digital system which improve a cost function such as energy consumption.
摘要翻译：描述了分层存储器的设计时数据分配技术的方法，装置和软件产品，例如。基本数字系统中的多存储存储器以及用于这种系统的运行时存储器管理技术的方法，装置和软件产品。描述了用于将数据分配给分层存储器的内存分配技术，特别是对于在运行时分配动态封装/删除任务的数据的多任务应用程序。分层存储器（诸如多存储器存储器）的能量消耗在很大程度上取决于数据如何被分配给存储器组。描述了分层存储器的设计时数据分配技术的方法，装置和软件产品，例如。在本质上数字系统中的多存储器，其改善诸如能量消耗的成本功能。

3. 发明专利

AU2003283140A1 COST-AWARE DESIGN-TIME/RUN-TIME MEMORY MANAGEMENT METHODS AND APPARATUS 未知
公开(公告)号：AU2003283140A1
公开(公告)日：2004-06-15
申请号：AU2003283140
申请日：2003-11-18
申请人： IMEC INTER UNI MICRO ELECTR
发明人： MARCHAL PAUL , GOMEZ JOSE IGNACIO , BRUNI DAVIDE , CATTHOOR FRANCKY
IPC分类号： G06F9/45
摘要： Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system as well as methods, apparatus and software products for run-time memory management techniques of such a system. Memory assignment techniques are described for assigning data to a hierarchical memory particularly for multi-tasked applications where data of dynamically created/deleted tasks is allocated at run-time. The energy consumption of hierarchical memories such as multi-banked memories depends largely on how data is assigned to the memory banks. Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system which improve a cost function such as energy consumption.

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